blob: f3883d3e94e5f9e1836041a7eab7f10280f7113b [file] [log] [blame]
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08001# Warning: This file is included whether or not the if is here.
2# The if controls how the evaluation occurs.
3# (See also src/Kconfig)
Alexandru Gagniucf64111b2013-12-13 20:44:48 -06006source src/cpu/allwinner/Kconfig
Hung-Te Lin7635a602013-02-12 00:07:38 +08007source src/cpu/armltd/Kconfig
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08008source src/cpu/samsung/Kconfig
Gabe Black3c7e9392013-05-26 07:15:57 -07009source src/cpu/ti/Kconfig
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -080010
11endif # ARCH_ARM
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000013if ARCH_X86
Ronald G. Minnich5f6572e2009-08-12 15:39:38 +000015source src/cpu/amd/Kconfig
Andrew Wu52e665b2013-06-19 18:55:08 +080016source src/cpu/dmp/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +000017source src/cpu/intel/Kconfig
18source src/cpu/via/Kconfig
Gerd Hoffmanncbf30732013-05-31 09:23:26 +020019source src/cpu/qemu-x86/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +000020source src/cpu/x86/Kconfig
Patrick Georgi0588d192009-08-12 15:00:51 +000021
Stefan Reinauer704b5962010-08-30 17:53:13 +000022config CACHE_AS_RAM
Patrick Georgi39ec29c2009-08-27 12:10:50 +000023 bool
Stefan Reinauer314e5512010-04-09 20:36:29 +000024 default !ROMCC
Patrick Georgi39ec29c2009-08-27 12:10:50 +000025
Patrick Georgi0588d192009-08-12 15:00:51 +000026config DCACHE_RAM_BASE
27 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000028
30 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000031
Stefan Reinauer2c41c402012-05-01 11:13:52 -070032# FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better
33# yet be dropped completely.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000034config MAX_PHYSICAL_CPUS
35 int
Stefan Reinauerd81744e2012-06-25 14:12:58 -070036 depends on CPU_AMD_MODEL_10XXX || CPU_AMD_MODEL_FXX || CPU_AMD_AGESA
Patrick Georgi0e9a9252009-10-06 20:48:07 +000037 default 1
Patrick Georgi0588d192009-08-12 15:00:51 +000039config SMP
40 bool
Myles Watson45bb25f2009-09-22 18:49:08 +000041 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +000042 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000043 help
44 This option is used to enable certain functions to make coreboot
45 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000046
Kyösti Mälkki7dfe32c2012-02-14 10:39:17 +020047config AP_SIPI_VECTOR
48 hex
49 default 0xfffff000
50 help
51 This must equal address of ap_sipi_vector from bootblock build.
Patrick Georgi819c7d42012-03-31 13:08:12 +020052
Ronald G. Minnich149d6752009-10-01 23:22:50 +000053config MMX
54 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000055 help
56 Select MMX in your socket or model Kconfig if your CPU has MMX
57 streaming SIMD instructions. ROMCC can build more efficient
58 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000059
60config SSE
61 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000062 help
63 Select SSE in your socket or model Kconfig if your CPU has SSE
64 streaming SIMD instructions. ROMCC can build more efficient
65 code if it can spill to SSE (aka XMM) registers.
67config SSE2
68 bool
Myles Watson34261952010-03-19 02:33:40 +000069 default n
Stefan Reinauera7acc512010-02-25 13:40:49 +000070 help
71 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
72 streaming SIMD instructions. Some parts of coreboot can be built
73 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000074
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000075endif # ARCH_X86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050076
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060077config SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050078 bool
79 default n
Alexandru Gagniuca406119e2013-12-04 21:57:15 -060081# This variable is used to determine if we add CPU microcode to CBFS during the
82# build. Microcode can be added manually afterwards, or removed. As a result,
83# code should not rely on this to tell if a microcode update is present or not,
84# and should instead search CBFS.
85# This variable is useful in determining if certain automated post-processing
86# steps can be performed right after the build, such as automatically adding
87# a firmware interface table.
89 bool
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050092choice
Stefan Reinauer9c29cfa2013-02-27 20:24:11 +010093 prompt "Include CPU microcode in CBFS" if ARCH_X86
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060094 default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050096
98 bool "Generate from tree"
99 help
100 Select this option if you want microcode updates to be assembled when
101 building coreboot and included in the final image as a separate CBFS
102 file. Microcode will not be hard-coded into ramstage.
Stefan Tauner0ce2b432013-04-01 13:45:44 +0200104 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500105 time with cbfstool, if desired.
107 If unsure, select this option.
110 bool "Include external microcode file"
111 help
112 Select this option if you want to include an external file containing
113 the CPU microcode. This will be included as a separate file in CBFS.
114 A word of caution: only select this option if you are sure the
115 microcode that you have is newer than the microcode shipping with
116 coreboot.
Stefan Tauner0ce2b432013-04-01 13:45:44 +0200118 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500119 time with cbfstool, if desired.
121 If unsure, select "Generate from tree"
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500123config CPU_MICROCODE_CBFS_NONE
124 bool "Do not include microcode updates"
125 help
126 Select this option if you do not want CPU microcode included in CBFS.
127 Note that for some CPUs, the microcode is hard-coded into the source
128 tree and is not loaded from CBFS. In this case, microcode will still
129 be updated. There is a push to move all microcode to CBFS, but this
130 change is not implemented for all CPUs.
132 This option currently applies to:
133 - Intel SandyBridge/IvyBridge
134 - VIA Nano
136 Microcode may be added to the ROM image at a later time with cbfstool,
137 if desired.
139 If unsure, select "Generate from tree"
141 The GOOD:
142 Microcode updates intend to solve issues that have been discovered
143 after CPU production. The expected effect is that systems work as
144 intended with the updated microcode, but we have also seen cases where
145 issues were solved by not applying microcode updates.
147 The BAD:
148 Note that some operating system include these same microcode patches,
149 so you may need to also disable microcode updates in your operating
150 system for this option to have an effect.
152 The UGLY:
153 A word of CAUTION: some CPUs depend on microcode updates to function
154 correctly. Not updating the microcode may leave the CPU operating at
155 less than optimal performance, or may cause outright hangups.
156 There are CPUs where coreboot cannot properly initialize the CPU
157 without microcode updates
158 For example, if running with the factory microcode, some Intel
159 SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
160 will hang when changing the frequency.
162 Make sure you have a way of flashing the ROM externally before
163 selecting this option.
Jens Rottmann686dc0d2013-02-18 17:26:01 +0100166
168 string "Path and filename of CPU microcode"
170 default "cpu_microcode.bin"
171 help
172 The path and filename of the file containing the CPU microcode.
Marc Jonesbdafcfa2013-10-29 17:46:54 -0600173
175 hex "Microcode address in CBFS"
176 depends on CPU_MICROCODE_IN_CBFS
177 default 0
180 hex "Microcode length in CBFS"
181 depends on CPU_MICROCODE_IN_CBFS
182 default 0xC000
183 help
184 The microcode needs a specific length to get correctly
185 detected and loaded by all CPUs.