blob: 8569af03ce3121169d33538e355ca744d072ad42 [file] [log] [blame]
Marc Jones54b8e7a2013-10-29 17:57:30 -06001##
2## This file is part of the coreboot project.
3##
Martin Roth18a40e02014-04-04 11:59:48 -06004## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
Marc Jones54b8e7a2013-10-29 17:57:30 -06005##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
Martin Roth18a40e02014-04-04 11:59:48 -060020ifneq ($(CONFIG_FSP_VENDORCODE_HEADER_PATH),)
Marc Jones54b8e7a2013-10-29 17:57:30 -060021FSP_PATH := $(call strip_quotes,$(CONFIG_FSP_VENDORCODE_HEADER_PATH))
Martin Roth18a40e02014-04-04 11:59:48 -060022FSP_SRC_FILES := $(wildcard src/vendorcode/intel/$(FSP_PATH)srx/*.c)
23FSP_C_INPUTS := $(foreach file, $(FSP_SRC_FILES), $(FSP_PATH)srx/$(notdir $(file)))
24ramstage-y += $(FSP_C_INPUTS)
25
Marc Jones54b8e7a2013-10-29 17:57:30 -060026CC := $(CC) -Isrc/vendorcode/intel/$(FSP_PATH)include
Martin Roth18a40e02014-04-04 11:59:48 -060027endif