blob: 634371b0aa40cae7bef2fe603c9f2dffa2739003 [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauer8e073822012-04-04 00:07:22 +02004 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of
8 * the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer8e073822012-04-04 00:07:22 +020014 */
15
16#include <console/console.h>
17#include <device/device.h>
18#include <device/pci.h>
Kyösti Mälkkidf128a52019-09-21 18:35:37 +030019#include <device/pci_def.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020020#include <device/pci_ops.h>
Stefan Reinauer8e073822012-04-04 00:07:22 +020021#include <device/pci_ids.h>
22#include "pch.h"
23
24static void pci_init(struct device *dev)
25{
26 u16 reg16;
27 u8 reg8;
28
29 printk(BIOS_DEBUG, "PCI init.\n");
30 /* Enable Bus Master */
31 reg16 = pci_read_config16(dev, PCI_COMMAND);
32 reg16 |= PCI_COMMAND_MASTER;
33 pci_write_config16(dev, PCI_COMMAND, reg16);
34
35 /* This device has no interrupt */
36 pci_write_config8(dev, INTR, 0xff);
37
38 /* disable parity error response and SERR */
Kyösti Mälkkidf128a52019-09-21 18:35:37 +030039 reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
40 reg16 &= ~PCI_BRIDGE_CTL_PARITY;
41 reg16 &= ~PCI_BRIDGE_CTL_SERR;
42 pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
Stefan Reinauer8e073822012-04-04 00:07:22 +020043
44 /* Master Latency Count must be set to 0x04! */
45 reg8 = pci_read_config8(dev, SMLT);
46 reg8 &= 0x07;
47 reg8 |= (0x04 << 3);
48 pci_write_config8(dev, SMLT, reg8);
49
Stefan Reinauer8e073822012-04-04 00:07:22 +020050 /* Clear errors in status registers */
51 reg16 = pci_read_config16(dev, PSTS);
52 //reg16 |= 0xf900;
53 pci_write_config16(dev, PSTS, reg16);
54
55 reg16 = pci_read_config16(dev, SECSTS);
56 // reg16 |= 0xf900;
57 pci_write_config16(dev, SECSTS, reg16);
58}
59
Stefan Reinauer8e073822012-04-04 00:07:22 +020060static struct pci_operations pci_ops = {
Kyösti Mälkkidbd31322019-03-20 17:55:27 +020061 .set_subsystem = pci_dev_set_subsystem,
Stefan Reinauer8e073822012-04-04 00:07:22 +020062};
63
64static struct device_operations device_ops = {
65 .read_resources = pci_bus_read_resources,
66 .set_resources = pci_dev_set_resources,
Kyösti Mälkkia84a7342019-09-23 10:01:16 +030067 .enable_resources = pci_bus_enable_resources,
Stefan Reinauer8e073822012-04-04 00:07:22 +020068 .init = pci_init,
69 .scan_bus = pci_scan_bridge,
70 .ops_pci = &pci_ops,
71};
72
73static const struct pci_driver pch_pci __pci_driver = {
74 .ops = &device_ops,
75 .vendor = PCI_VENDOR_ID_INTEL,
76 .device = 0x2448,
77};