Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 12d010306b3892b01350e96d83275206215d9f31 / . / src / southbridge / intel / i82801jx / smbus.c
blob: 00894cf82a26f9ee48e42c0d51d83666b0921c5f [file] [log] [blame]
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <console/console.h>
18#include <device/device.h>
19#include <device/path.h>
20#include <device/smbus.h>
21#include <device/pci.h>
22#include <device/pci_ids.h>
23#include <device/pci_ops.h>
24#include <arch/io.h>
25#include "smbus.h"
26
27static void pch_smbus_init(device_t dev)
28{
29 u16 reg16;
30
31 /* Enable clock gating */
32 reg16 = pci_read_config16(dev, 0x80);
33 reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
34 pci_write_config16(dev, 0x80, reg16);
35}
36
37static int lsmbus_read_byte(device_t dev, u8 address)
38{
39 u16 device;
40 struct resource *res;
41 struct bus *pbus;
42
43 device = dev->path.i2c.device;
44 pbus = get_pbus_smbus(dev);
45 res = find_resource(pbus->dev, 0x20);
46
47 return do_smbus_read_byte(res->base, device, address);
48}
49
50static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
51{
52 u16 device;
53 struct resource *res;
54 struct bus *pbus;
55
56 device = dev->path.i2c.device;
57 pbus = get_pbus_smbus(dev);
58 res = find_resource(pbus->dev, 0x20);
59
60 return do_smbus_write_byte(res->base, device, address, val);
61}
62
63static struct smbus_bus_operations lops_smbus_bus = {
64 .read_byte = lsmbus_read_byte,
65 .write_byte = lsmbus_write_byte,
66};
67
68static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
69{
70 if (!vendor || !device) {
71 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
72 pci_read_config32(dev, PCI_VENDOR_ID));
73 } else {
74 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
75 ((device & 0xffff) << 16) | (vendor & 0xffff));
76 }
77}
78
79static struct pci_operations smbus_pci_ops = {
80 .set_subsystem = smbus_set_subsystem,
81};
82
83static void smbus_read_resources(device_t dev)
84{
85 struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
86 res->base = SMBUS_IO_BASE;
87 res->size = 32;
88 res->limit = res->base + res->size - 1;
89 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
90 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
91
92 /* Also add MMIO resource */
93 res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
94}
95
96static struct device_operations smbus_ops = {
97 .read_resources = smbus_read_resources,
98 .set_resources = pci_dev_set_resources,
99 .enable_resources = pci_dev_enable_resources,
100 .scan_bus = scan_smbus,
101 .init = pch_smbus_init,
102 .ops_smbus_bus = &lops_smbus_bus,
103 .ops_pci = &smbus_pci_ops,
104};
105
Arthur Heymans349e0852017-04-09 20:48:37 +0200[diff] [blame]106static const unsigned short pci_device_ids[] =
107{
108 0x3a30,
109 0x3a60,
110 0
111};
Arthur Heymans7b9c1392017-04-09 20:40:39 +0200[diff] [blame]112
113static const struct pci_driver pch_smbus __pci_driver = {
114 .ops = &smbus_ops,
115 .vendor = PCI_VENDOR_ID_INTEL,
116 .devices = pci_device_ids,
117};