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Marc Bertens2ad8ab82010-06-04 19:53:55 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Marc Bertens2ad8ab82010-06-04 19:53:55 +000015 */
Uwe Hermannc6a10622010-10-17 19:30:58 +000016
Marc Bertens2ad8ab82010-06-04 19:53:55 +000017#include <device/device.h>
18#include <device/pci.h>
19#include <device/pci_ids.h>
20#include <device/pci_ops.h>
Sven Schnelle5c72a872011-04-20 08:58:30 +000021#include <device/cardbus.h>
Marc Bertens2ad8ab82010-06-04 19:53:55 +000022#include <console/console.h>
Sven Schnellebaec0342011-04-20 08:57:53 +000023#include "chip.h"
Marc Bertens2ad8ab82010-06-04 19:53:55 +000024
25static void ti_pci1x2y_init(struct device *dev)
26{
Uwe Hermann2d1d9ceb2010-12-26 14:12:38 +000027
Sven Schnellebaec0342011-04-20 08:57:53 +000028 printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
29 struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
30
31 if (conf) {
Sven Schnellebaec0342011-04-20 08:57:53 +000032 /* System control (offset 0x80) */
33 pci_write_config32(dev, 0x80, conf->scr);
34 /* Multifunction routing */
35 pci_write_config32(dev, 0x8C, conf->mrr);
36 }
Uwe Hermann2d1d9ceb2010-12-26 14:12:38 +000037 /* Set the device control register (0x92) accordingly. */
38 pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
Marc Bertens2ad8ab82010-06-04 19:53:55 +000039}
40
Elyes HAOUASa3970892018-05-19 10:39:20 +020041static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor,
42 unsigned device)
Sven Schnelle5f22f3032011-04-20 08:58:16 +000043{
44 /*
45 * Enable change sub-vendor ID. Clear the bit 5 to enable to write
46 * to the sub-vendor/device ids at 40 and 42.
47 */
48 pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10);
49 pci_write_config16(dev, 0x40, vendor);
50 pci_write_config16(dev, 0x42, device);
51 pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10);
52}
53
54static struct pci_operations ti_pci1x2y_pci_ops = {
55 .set_subsystem = ti_pci1x2y_set_subsystem,
56};
57
Sven Schnellebaec0342011-04-20 08:57:53 +000058struct device_operations southbridge_ti_pci1x2x_pciops = {
Sven Schnelle5c72a872011-04-20 08:58:30 +000059 .read_resources = cardbus_read_resources,
Marc Bertens2ad8ab82010-06-04 19:53:55 +000060 .set_resources = pci_dev_set_resources,
Sven Schnelle5c72a872011-04-20 08:58:30 +000061 .enable_resources = cardbus_enable_resources,
Marc Bertens2ad8ab82010-06-04 19:53:55 +000062 .init = ti_pci1x2y_init,
63 .scan_bus = 0,
Sven Schnelle5f22f3032011-04-20 08:58:16 +000064 .ops_pci = &ti_pci1x2y_pci_ops,
Marc Bertens2ad8ab82010-06-04 19:53:55 +000065};
66
Marc Bertens2ad8ab82010-06-04 19:53:55 +000067static const struct pci_driver ti_pci1225_driver __pci_driver = {
Sven Schnellebaec0342011-04-20 08:57:53 +000068 .ops = &southbridge_ti_pci1x2x_pciops,
Uwe Hermann2d1d9ceb2010-12-26 14:12:38 +000069 .vendor = PCI_VENDOR_ID_TI,
70 .device = PCI_DEVICE_ID_TI_1225,
Marc Bertens2ad8ab82010-06-04 19:53:55 +000071};
72
Marc Bertens2ad8ab82010-06-04 19:53:55 +000073static const struct pci_driver ti_pci1420_driver __pci_driver = {
Sven Schnellebaec0342011-04-20 08:57:53 +000074 .ops = &southbridge_ti_pci1x2x_pciops,
Uwe Hermann2d1d9ceb2010-12-26 14:12:38 +000075 .vendor = PCI_VENDOR_ID_TI,
76 .device = PCI_DEVICE_ID_TI_1420,
Marc Bertens2ad8ab82010-06-04 19:53:55 +000077};
Myles Watson356f8482010-06-07 20:15:54 +000078
Sven Schnelle20f7f3b2011-04-20 08:58:08 +000079static const struct pci_driver ti_pci1510_driver __pci_driver = {
80 .ops = &southbridge_ti_pci1x2x_pciops,
81 .vendor = PCI_VENDOR_ID_TI,
82 .device = PCI_DEVICE_ID_TI_1510,
83};
84
Marc Bertens2ad8ab82010-06-04 19:53:55 +000085static const struct pci_driver ti_pci1520_driver __pci_driver = {
Sven Schnellebaec0342011-04-20 08:57:53 +000086 .ops = &southbridge_ti_pci1x2x_pciops,
Uwe Hermann2d1d9ceb2010-12-26 14:12:38 +000087 .vendor = PCI_VENDOR_ID_TI,
88 .device = PCI_DEVICE_ID_TI_1520,
Marc Bertens2ad8ab82010-06-04 19:53:55 +000089};
Sven Schnellebaec0342011-04-20 08:57:53 +000090
91struct chip_operations southbridge_ti_pci1x2x_ops = {
92 CHIP_NAME("TI PCI1x2x Cardbus controller")
93};