Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 15 | */ |
Uwe Hermann | c6a1062 | 2010-10-17 19:30:58 +0000 | [diff] [blame] | 16 | |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <device/pci_ops.h> |
Sven Schnelle | 5c72a87 | 2011-04-20 08:58:30 +0000 | [diff] [blame] | 21 | #include <device/cardbus.h> |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 22 | #include <console/console.h> |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 23 | #include "chip.h" |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 24 | |
| 25 | static void ti_pci1x2y_init(struct device *dev) |
| 26 | { |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 27 | |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 28 | printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); |
| 29 | struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; |
| 30 | |
| 31 | if (conf) { |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 32 | /* System control (offset 0x80) */ |
| 33 | pci_write_config32(dev, 0x80, conf->scr); |
| 34 | /* Multifunction routing */ |
| 35 | pci_write_config32(dev, 0x8C, conf->mrr); |
| 36 | } |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 37 | /* Set the device control register (0x92) accordingly. */ |
| 38 | pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 39 | } |
| 40 | |
Elyes HAOUAS | a397089 | 2018-05-19 10:39:20 +0200 | [diff] [blame] | 41 | static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor, |
| 42 | unsigned device) |
Sven Schnelle | 5f22f303 | 2011-04-20 08:58:16 +0000 | [diff] [blame] | 43 | { |
| 44 | /* |
| 45 | * Enable change sub-vendor ID. Clear the bit 5 to enable to write |
| 46 | * to the sub-vendor/device ids at 40 and 42. |
| 47 | */ |
| 48 | pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10); |
| 49 | pci_write_config16(dev, 0x40, vendor); |
| 50 | pci_write_config16(dev, 0x42, device); |
| 51 | pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10); |
| 52 | } |
| 53 | |
| 54 | static struct pci_operations ti_pci1x2y_pci_ops = { |
| 55 | .set_subsystem = ti_pci1x2y_set_subsystem, |
| 56 | }; |
| 57 | |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 58 | struct device_operations southbridge_ti_pci1x2x_pciops = { |
Sven Schnelle | 5c72a87 | 2011-04-20 08:58:30 +0000 | [diff] [blame] | 59 | .read_resources = cardbus_read_resources, |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 60 | .set_resources = pci_dev_set_resources, |
Sven Schnelle | 5c72a87 | 2011-04-20 08:58:30 +0000 | [diff] [blame] | 61 | .enable_resources = cardbus_enable_resources, |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 62 | .init = ti_pci1x2y_init, |
| 63 | .scan_bus = 0, |
Sven Schnelle | 5f22f303 | 2011-04-20 08:58:16 +0000 | [diff] [blame] | 64 | .ops_pci = &ti_pci1x2y_pci_ops, |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 65 | }; |
| 66 | |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 67 | static const struct pci_driver ti_pci1225_driver __pci_driver = { |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 68 | .ops = &southbridge_ti_pci1x2x_pciops, |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 69 | .vendor = PCI_VENDOR_ID_TI, |
| 70 | .device = PCI_DEVICE_ID_TI_1225, |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 71 | }; |
| 72 | |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 73 | static const struct pci_driver ti_pci1420_driver __pci_driver = { |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 74 | .ops = &southbridge_ti_pci1x2x_pciops, |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 75 | .vendor = PCI_VENDOR_ID_TI, |
| 76 | .device = PCI_DEVICE_ID_TI_1420, |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 77 | }; |
Myles Watson | 356f848 | 2010-06-07 20:15:54 +0000 | [diff] [blame] | 78 | |
Sven Schnelle | 20f7f3b | 2011-04-20 08:58:08 +0000 | [diff] [blame] | 79 | static const struct pci_driver ti_pci1510_driver __pci_driver = { |
| 80 | .ops = &southbridge_ti_pci1x2x_pciops, |
| 81 | .vendor = PCI_VENDOR_ID_TI, |
| 82 | .device = PCI_DEVICE_ID_TI_1510, |
| 83 | }; |
| 84 | |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 85 | static const struct pci_driver ti_pci1520_driver __pci_driver = { |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 86 | .ops = &southbridge_ti_pci1x2x_pciops, |
Uwe Hermann | 2d1d9ceb | 2010-12-26 14:12:38 +0000 | [diff] [blame] | 87 | .vendor = PCI_VENDOR_ID_TI, |
| 88 | .device = PCI_DEVICE_ID_TI_1520, |
Marc Bertens | 2ad8ab8 | 2010-06-04 19:53:55 +0000 | [diff] [blame] | 89 | }; |
Sven Schnelle | baec034 | 2011-04-20 08:57:53 +0000 | [diff] [blame] | 90 | |
| 91 | struct chip_operations southbridge_ti_pci1x2x_ops = { |
| 92 | CHIP_NAME("TI PCI1x2x Cardbus controller") |
| 93 | }; |