Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
Ronald G. Minnich | 42acd12 | 2003-09-26 17:41:21 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Enable the serial evices on the VIA |
| 4 | */ |
| 5 | |
| 6 | |
| 7 | /* The base address is 0x15c, 0x2e, depending on config bytes */ |
| 8 | |
| 9 | #define SIO_BASE 0x3f0 |
| 10 | #define SIO_DATA SIO_BASE+1 |
| 11 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 12 | static void vt8231_writesuper(uint8_t reg, uint8_t val) |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 13 | { |
| 14 | outb(reg, SIO_BASE); |
| 15 | outb(val, SIO_DATA); |
Ronald G. Minnich | 42acd12 | 2003-09-26 17:41:21 +0000 | [diff] [blame] | 16 | } |
| 17 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 18 | static void vt8231_writesiobyte(uint16_t reg, uint8_t val) |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 19 | { |
| 20 | outb(val, reg); |
Ronald G. Minnich | 42acd12 | 2003-09-26 17:41:21 +0000 | [diff] [blame] | 21 | } |
| 22 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 23 | static void vt8231_writesioword(uint16_t reg, uint16_t val) |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 24 | { |
| 25 | outw(val, reg); |
Ronald G. Minnich | 42acd12 | 2003-09-26 17:41:21 +0000 | [diff] [blame] | 26 | } |
| 27 | |
| 28 | |
| 29 | /* regs we use: 85, and the southbridge devfn is defined by the |
| 30 | mainboard |
| 31 | */ |
| 32 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 33 | static void enable_vt8231_serial(void) |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 34 | { |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 35 | uint8_t c; |
| 36 | device_t dev; |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 37 | post_code(0x06); |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 38 | dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 39 | |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 40 | if (dev == PCI_DEV_INVALID) { |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 41 | post_code(0x07); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 42 | die("Serial controller not found\n"); |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 43 | } |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 44 | |
| 45 | /* first, you have to enable the superio and superio config. |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 46 | put a 6 reg 80 |
| 47 | */ |
| 48 | c = pci_read_config8(dev, 0x50); |
| 49 | c |= 6; |
| 50 | pci_write_config8(dev, 0x50, c); |
Alexandru Gagniuc | 5005bb06 | 2011-04-11 20:17:22 +0000 | [diff] [blame] | 51 | post_code(0x02); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 52 | // now go ahead and set up com1. |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 53 | // set address |
| 54 | vt8231_writesuper(0xf4, 0xfe); |
| 55 | // enable serial out |
| 56 | vt8231_writesuper(0xf2, 7); |
| 57 | // That's it for the sio stuff. |
| 58 | // movl $SUPERIOCONFIG, %eax |
| 59 | // movb $9, %dl |
| 60 | // PCI_WRITE_CONFIG_BYTE |
| 61 | // set up reg to set baud rate. |
| 62 | vt8231_writesiobyte(0x3fb, 0x80); |
| 63 | // Set 115 kb |
| 64 | vt8231_writesioword(0x3f8, 1); |
| 65 | // Set 9.6 kb |
| 66 | // WRITESIOWORD(0x3f8, 12) |
| 67 | // now set no parity, one stop, 8 bits |
| 68 | vt8231_writesiobyte(0x3fb, 3); |
| 69 | // now turn on RTS, DRT |
| 70 | vt8231_writesiobyte(0x3fc, 3); |
| 71 | // Enable interrupts |
| 72 | vt8231_writesiobyte(0x3f9, 0xf); |
| 73 | // should be done. Dump a char for fun. |
| 74 | vt8231_writesiobyte(0x3f8, 48); |
Ronald G. Minnich | 42acd12 | 2003-09-26 17:41:21 +0000 | [diff] [blame] | 75 | } |