Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <soc/addressmap.h> |
| 21 | #include <soc/clock.h> |
| 22 | #include <soc/emc.h> |
| 23 | #include <soc/mc.h> |
| 24 | #include <soc/pmc.h> |
| 25 | #include <soc/sdram.h> |
| 26 | #include <stdlib.h> |
| 27 | #include <soc/nvidia/tegra/apbmisc.h> |
| 28 | |
| 29 | static void sdram_patch(uintptr_t addr, uint32_t value) |
| 30 | { |
| 31 | if (addr) |
| 32 | write32((uint32_t *)addr, value); |
| 33 | } |
| 34 | |
| 35 | static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) |
| 36 | { |
| 37 | clrsetbits_le32(addr, mask, (value & mask)); |
| 38 | } |
| 39 | |
| 40 | static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) |
| 41 | { |
| 42 | write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); |
| 43 | } |
| 44 | |
| 45 | /* PMC must be configured before clock-enable and de-reset of MC/EMC. */ |
| 46 | static void sdram_configure_pmc(const struct sdram_params *param, |
| 47 | struct tegra_pmc_regs *regs) |
| 48 | { |
| 49 | /* VDDP Select */ |
| 50 | write32(®s->vddp_sel, param->PmcVddpSel); |
| 51 | udelay(param->PmcVddpSelWait); |
| 52 | |
| 53 | /* Set DDR pad voltage */ |
| 54 | writebits(param->PmcDdrPwr, ®s->ddr_pwr, PMC_DDR_PWR_VAL_MASK); |
| 55 | |
| 56 | /* Turn on MEM IO Power */ |
| 57 | writebits(param->PmcNoIoPower, ®s->no_iopower, |
| 58 | (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); |
| 59 | |
| 60 | write32(®s->reg_short, param->PmcRegShort); |
| 61 | write32(®s->ddr_cntrl, param->PmcDdrCntrl); |
| 62 | } |
| 63 | |
| 64 | static void sdram_set_ddr_control(const struct sdram_params *param, |
| 65 | struct tegra_pmc_regs *regs) |
| 66 | { |
| 67 | u32 ddrcntrl = read32(®s->ddr_cntrl); |
| 68 | |
| 69 | /* Deassert HOLD_CKE_LOW */ |
| 70 | ddrcntrl &= ~PMC_CMD_HOLD_LOW_BR00_11_MASK; |
| 71 | write32(®s->ddr_cntrl, ddrcntrl); |
| 72 | udelay(param->PmcDdrCntrlWait); |
| 73 | } |
| 74 | |
| 75 | static void sdram_start_clocks(const struct sdram_params *param, |
| 76 | struct tegra_emc_regs *regs) |
| 77 | { |
| 78 | struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; |
| 79 | |
| 80 | u32 is_same_freq = (param->McEmemArbMisc0 & |
| 81 | MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0; |
| 82 | u32 clk_source_emc = param->EmcClockSource; |
| 83 | |
| 84 | /* Enable the clocks for EMC and MC */ |
| 85 | setbits_le32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC |
| 86 | setbits_le32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC |
| 87 | |
| 88 | if ((clk_source_emc >> EMC_2X_CLK_SRC_SHIFT) != PLLM_UD) |
| 89 | setbits_le32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL); |
| 90 | |
| 91 | /* Remove the EMC and MC controllers from reset */ |
| 92 | clrbits_le32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC |
| 93 | clrbits_le32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC |
| 94 | |
| 95 | clk_source_emc |= (is_same_freq << 16); |
| 96 | |
| 97 | write32(&clk_rst->clk_src_emc, clk_source_emc); |
| 98 | write32(&clk_rst->clk_src_emc_dll, param->EmcClockSourceDll); |
| 99 | |
| 100 | clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider, |
| 101 | param->PllMPostDivider, param->PllMSetupControl, |
| 102 | param->PllMKVCO, param->PllMKCP, param->PllMStableTime, |
| 103 | param->EmcClockSource, is_same_freq); |
| 104 | |
| 105 | if (param->ClkRstControllerPllmMisc2OverrideEnable) |
| 106 | write32(&clk_rst->pllm_misc2, |
| 107 | param->ClkRstControllerPllmMisc2Override); |
| 108 | |
| 109 | /* Wait for enough time for clk switch to take place */ |
| 110 | udelay(5); |
| 111 | |
| 112 | write32(&clk_rst->clk_enb_w_clr, param->ClearClk2Mc1); |
| 113 | } |
| 114 | |
| 115 | static void sdram_set_swizzle(const struct sdram_params *param, |
| 116 | struct tegra_emc_regs *regs) |
| 117 | { |
| 118 | write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); |
| 119 | write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); |
| 120 | write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); |
| 121 | write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); |
| 122 | |
| 123 | write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); |
| 124 | write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); |
| 125 | write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); |
| 126 | write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); |
| 127 | } |
| 128 | |
| 129 | static void sdram_set_pad_controls(const struct sdram_params *param, |
| 130 | struct tegra_emc_regs *regs) |
| 131 | { |
| 132 | /* Program the pad controls */ |
| 133 | write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); |
| 134 | write32(®s->xm2comppadctrl2, param->EmcXm2CompPadCtrl2); |
| 135 | write32(®s->xm2comppadctrl3, param->EmcXm2CompPadCtrl3); |
| 136 | } |
| 137 | |
| 138 | static void sdram_set_pad_macros(const struct sdram_params *param, |
| 139 | struct tegra_emc_regs *regs) |
| 140 | { |
| 141 | u32 rfu_reset, rfu_mask1, rfu_mask2, rfu_step1, rfu_step2; |
| 142 | u32 cpm_reset_settings, cpm_mask1, cpm_step1; |
| 143 | |
| 144 | write32(®s->pmacro_vttgen_ctrl0, param->EmcPmacroVttgenCtrl0); |
| 145 | write32(®s->pmacro_vttgen_ctrl1, param->EmcPmacroVttgenCtrl1); |
| 146 | write32(®s->pmacro_vttgen_ctrl2, param->EmcPmacroVttgenCtrl2); |
| 147 | /* Trigger timing update so above writes take place */ |
| 148 | sdram_trigger_emc_timing_update(regs); |
| 149 | /* Add a wait to ensure the regulators settle */ |
| 150 | udelay(10); |
| 151 | |
| 152 | write32(®s->dbg, |
| 153 | param->EmcDbg | (param->EmcDbgWriteMux & WRITE_MUX_ACTIVE)); |
| 154 | |
| 155 | rfu_reset = EMC_PMACRO_BRICK_CTRL_RFU1_RESET_VAL; |
| 156 | rfu_mask1 = 0x01120112; |
| 157 | rfu_mask2 = 0x01BF01BF; |
| 158 | |
| 159 | rfu_step1 = rfu_reset & (param->EmcPmacroBrickCtrlRfu1 | ~rfu_mask1); |
| 160 | rfu_step2 = rfu_reset & (param->EmcPmacroBrickCtrlRfu1 | ~rfu_mask2); |
| 161 | |
| 162 | /* common pad macro (cpm) */ |
| 163 | cpm_reset_settings = 0x0000000F; |
| 164 | cpm_mask1 = 0x00000001; |
| 165 | cpm_step1 = cpm_reset_settings; |
| 166 | cpm_step1 &= (param->EmcPmacroCommonPadTxCtrl | ~cpm_mask1); |
| 167 | |
| 168 | /* Patch 2 using BCT spare variables */ |
| 169 | sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3); |
| 170 | |
| 171 | /* |
| 172 | * Program CMD mapping. Required before brick mapping, else |
| 173 | * we can't gaurantee CK will be differential at all times. |
| 174 | */ |
| 175 | write32(®s->fbio_cfg7, param->EmcFbioCfg7); |
| 176 | |
| 177 | write32(®s->cmd_mapping_cmd0_0, param->EmcCmdMappingCmd0_0); |
| 178 | write32(®s->cmd_mapping_cmd0_1, param->EmcCmdMappingCmd0_1); |
| 179 | write32(®s->cmd_mapping_cmd0_2, param->EmcCmdMappingCmd0_2); |
| 180 | write32(®s->cmd_mapping_cmd1_0, param->EmcCmdMappingCmd1_0); |
| 181 | write32(®s->cmd_mapping_cmd1_1, param->EmcCmdMappingCmd1_1); |
| 182 | write32(®s->cmd_mapping_cmd1_2, param->EmcCmdMappingCmd1_2); |
| 183 | write32(®s->cmd_mapping_cmd2_0, param->EmcCmdMappingCmd2_0); |
| 184 | write32(®s->cmd_mapping_cmd2_1, param->EmcCmdMappingCmd2_1); |
| 185 | write32(®s->cmd_mapping_cmd2_2, param->EmcCmdMappingCmd2_2); |
| 186 | write32(®s->cmd_mapping_cmd3_0, param->EmcCmdMappingCmd3_0); |
| 187 | write32(®s->cmd_mapping_cmd3_1, param->EmcCmdMappingCmd3_1); |
| 188 | write32(®s->cmd_mapping_cmd3_2, param->EmcCmdMappingCmd3_2); |
| 189 | write32(®s->cmd_mapping_byte, param->EmcCmdMappingByte); |
| 190 | |
| 191 | /* Program brick mapping. */ |
| 192 | write32(®s->pmacro_brick_mapping0, param->EmcPmacroBrickMapping0); |
| 193 | write32(®s->pmacro_brick_mapping1, param->EmcPmacroBrickMapping1); |
| 194 | write32(®s->pmacro_brick_mapping2, param->EmcPmacroBrickMapping2); |
| 195 | |
| 196 | write32(®s->pmacro_brick_ctrl_rfu1, rfu_step1); |
| 197 | |
| 198 | /* This is required to do any reads from the pad macros */ |
| 199 | write32(®s->config_sample_delay, param->EmcConfigSampleDelay); |
| 200 | |
| 201 | write32(®s->fbio_cfg8, param->EmcFbioCfg8); |
| 202 | |
| 203 | sdram_set_swizzle(param, regs); |
| 204 | |
| 205 | /* Patch 4 using BCT spare variables */ |
| 206 | sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7); |
| 207 | |
| 208 | sdram_set_pad_controls(param, regs); |
| 209 | |
| 210 | /* Program Autocal controls with shadowed register fields */ |
| 211 | write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); |
| 212 | write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); |
| 213 | write32(®s->auto_cal_config4, param->EmcAutoCalConfig4); |
| 214 | write32(®s->auto_cal_config5, param->EmcAutoCalConfig5); |
| 215 | write32(®s->auto_cal_config6, param->EmcAutoCalConfig6); |
| 216 | write32(®s->auto_cal_config7, param->EmcAutoCalConfig7); |
| 217 | write32(®s->auto_cal_config8, param->EmcAutoCalConfig8); |
| 218 | |
| 219 | write32(®s->pmacro_rx_term, param->EmcPmacroRxTerm); |
| 220 | write32(®s->pmacro_dq_tx_drv, param->EmcPmacroDqTxDrv); |
| 221 | write32(®s->pmacro_ca_tx_drv, param->EmcPmacroCaTxDrv); |
| 222 | write32(®s->pmacro_cmd_tx_drv, param->EmcPmacroCmdTxDrv); |
| 223 | write32(®s->pmacro_autocal_cfg_common, |
| 224 | param->EmcPmacroAutocalCfgCommon); |
| 225 | write32(®s->auto_cal_channel, param->EmcAutoCalChannel); |
| 226 | write32(®s->pmacro_zctrl, param->EmcPmacroZctrl); |
| 227 | |
| 228 | write32(®s->dll_cfg0, param->EmcDllCfg0); |
| 229 | write32(®s->dll_cfg1, param->EmcDllCfg1); |
| 230 | write32(®s->cfg_dig_dll_1, param->EmcCfgDigDll_1); |
| 231 | |
| 232 | write32(®s->data_brlshft_0, param->EmcDataBrlshft0); |
| 233 | write32(®s->data_brlshft_1, param->EmcDataBrlshft1); |
| 234 | write32(®s->dqs_brlshft_0, param->EmcDqsBrlshft0); |
| 235 | write32(®s->dqs_brlshft_1, param->EmcDqsBrlshft1); |
| 236 | write32(®s->cmd_brlshft_0, param->EmcCmdBrlshft0); |
| 237 | write32(®s->cmd_brlshft_1, param->EmcCmdBrlshft1); |
| 238 | write32(®s->cmd_brlshft_2, param->EmcCmdBrlshft2); |
| 239 | write32(®s->cmd_brlshft_3, param->EmcCmdBrlshft3); |
| 240 | write32(®s->quse_brlshft_0, param->EmcQuseBrlshft0); |
| 241 | write32(®s->quse_brlshft_1, param->EmcQuseBrlshft1); |
| 242 | write32(®s->quse_brlshft_2, param->EmcQuseBrlshft2); |
| 243 | write32(®s->quse_brlshft_3, param->EmcQuseBrlshft3); |
| 244 | |
| 245 | write32(®s->pmacro_brick_ctrl_rfu1, rfu_step2); |
| 246 | write32(®s->pmacro_pad_cfg_ctrl, param->EmcPmacroPadCfgCtrl); |
| 247 | |
| 248 | write32(®s->pmacro_pad_cfg_ctrl, param->EmcPmacroPadCfgCtrl); |
| 249 | write32(®s->pmacro_cmd_brick_ctrl_fdpd, |
| 250 | param->EmcPmacroCmdBrickCtrlFdpd); |
| 251 | write32(®s->pmacro_brick_ctrl_rfu2, |
| 252 | param->EmcPmacroBrickCtrlRfu2 & 0xFF7FFF7F); |
| 253 | write32(®s->pmacro_data_brick_ctrl_fdpd, |
| 254 | param->EmcPmacroDataBrickCtrlFdpd); |
| 255 | write32(®s->pmacro_bg_bias_ctrl_0, param->EmcPmacroBgBiasCtrl0); |
| 256 | write32(®s->pmacro_data_pad_rx_ctrl, param->EmcPmacroDataPadRxCtrl); |
| 257 | write32(®s->pmacro_cmd_pad_rx_ctrl, param->EmcPmacroCmdPadRxCtrl); |
| 258 | write32(®s->pmacro_data_pad_tx_ctrl, param->EmcPmacroDataPadTxCtrl); |
| 259 | write32(®s->pmacro_data_rx_term_mode, |
| 260 | param->EmcPmacroDataRxTermMode); |
| 261 | write32(®s->pmacro_cmd_rx_term_mode, param->EmcPmacroCmdRxTermMode); |
| 262 | write32(®s->pmacro_cmd_pad_tx_ctrl, param->EmcPmacroCmdPadTxCtrl); |
| 263 | |
| 264 | write32(®s->cfg_3, param->EmcCfg3); |
| 265 | write32(®s->pmacro_tx_pwrd_0, param->EmcPmacroTxPwrd0); |
| 266 | write32(®s->pmacro_tx_pwrd_1, param->EmcPmacroTxPwrd1); |
| 267 | write32(®s->pmacro_tx_pwrd_2, param->EmcPmacroTxPwrd2); |
| 268 | write32(®s->pmacro_tx_pwrd_3, param->EmcPmacroTxPwrd3); |
| 269 | write32(®s->pmacro_tx_pwrd_4, param->EmcPmacroTxPwrd4); |
| 270 | write32(®s->pmacro_tx_pwrd_5, param->EmcPmacroTxPwrd5); |
| 271 | write32(®s->pmacro_tx_sel_clk_src_0, param->EmcPmacroTxSelClkSrc0); |
| 272 | write32(®s->pmacro_tx_sel_clk_src_1, param->EmcPmacroTxSelClkSrc1); |
| 273 | write32(®s->pmacro_tx_sel_clk_src_2, param->EmcPmacroTxSelClkSrc2); |
| 274 | write32(®s->pmacro_tx_sel_clk_src_3, param->EmcPmacroTxSelClkSrc3); |
| 275 | write32(®s->pmacro_tx_sel_clk_src_4, param->EmcPmacroTxSelClkSrc4); |
| 276 | write32(®s->pmacro_tx_sel_clk_src_5, param->EmcPmacroTxSelClkSrc5); |
| 277 | write32(®s->pmacro_ddll_bypass, param->EmcPmacroDdllBypass); |
| 278 | write32(®s->pmacro_ddll_pwrd_0, param->EmcPmacroDdllPwrd0); |
| 279 | write32(®s->pmacro_ddll_pwrd_1, param->EmcPmacroDdllPwrd1); |
| 280 | write32(®s->pmacro_ddll_pwrd_2, param->EmcPmacroDdllPwrd2); |
| 281 | write32(®s->pmacro_cmd_ctrl_0, param->EmcPmacroCmdCtrl0); |
| 282 | write32(®s->pmacro_cmd_ctrl_1, param->EmcPmacroCmdCtrl1); |
| 283 | write32(®s->pmacro_cmd_ctrl_2, param->EmcPmacroCmdCtrl2); |
| 284 | write32(®s->pmacro_ib_vref_dq_0, param->EmcPmacroIbVrefDq_0); |
| 285 | write32(®s->pmacro_ib_vref_dq_1, param->EmcPmacroIbVrefDq_1); |
| 286 | write32(®s->pmacro_ib_vref_dqs_0, param->EmcPmacroIbVrefDqs_0); |
| 287 | write32(®s->pmacro_ib_vref_dqs_1, param->EmcPmacroIbVrefDqs_1); |
| 288 | write32(®s->pmacro_ib_rxrt, param->EmcPmacroIbRxrt); |
| 289 | write32(®s->pmacro_quse_ddll_rank0_0, |
| 290 | param->EmcPmacroQuseDdllRank0_0); |
| 291 | write32(®s->pmacro_quse_ddll_rank0_1, |
| 292 | param->EmcPmacroQuseDdllRank0_1); |
| 293 | write32(®s->pmacro_quse_ddll_rank0_2, |
| 294 | param->EmcPmacroQuseDdllRank0_2); |
| 295 | write32(®s->pmacro_quse_ddll_rank0_3, |
| 296 | param->EmcPmacroQuseDdllRank0_3); |
| 297 | write32(®s->pmacro_quse_ddll_rank0_4, |
| 298 | param->EmcPmacroQuseDdllRank0_4); |
| 299 | write32(®s->pmacro_quse_ddll_rank0_5, |
| 300 | param->EmcPmacroQuseDdllRank0_5); |
| 301 | write32(®s->pmacro_quse_ddll_rank1_0, |
| 302 | param->EmcPmacroQuseDdllRank1_0); |
| 303 | write32(®s->pmacro_quse_ddll_rank1_1, |
| 304 | param->EmcPmacroQuseDdllRank1_1); |
| 305 | write32(®s->pmacro_quse_ddll_rank1_2, |
| 306 | param->EmcPmacroQuseDdllRank1_2); |
| 307 | write32(®s->pmacro_quse_ddll_rank1_3, |
| 308 | param->EmcPmacroQuseDdllRank1_3); |
| 309 | write32(®s->pmacro_quse_ddll_rank1_4, |
| 310 | param->EmcPmacroQuseDdllRank1_4); |
| 311 | write32(®s->pmacro_quse_ddll_rank1_5, |
| 312 | param->EmcPmacroQuseDdllRank1_5); |
| 313 | write32(®s->pmacro_brick_ctrl_rfu1, param->EmcPmacroBrickCtrlRfu1); |
| 314 | write32(®s->pmacro_ob_ddll_long_dq_rank0_0, |
| 315 | param->EmcPmacroObDdllLongDqRank0_0); |
| 316 | write32(®s->pmacro_ob_ddll_long_dq_rank0_1, |
| 317 | param->EmcPmacroObDdllLongDqRank0_1); |
| 318 | write32(®s->pmacro_ob_ddll_long_dq_rank0_2, |
| 319 | param->EmcPmacroObDdllLongDqRank0_2); |
| 320 | write32(®s->pmacro_ob_ddll_long_dq_rank0_3, |
| 321 | param->EmcPmacroObDdllLongDqRank0_3); |
| 322 | write32(®s->pmacro_ob_ddll_long_dq_rank0_4, |
| 323 | param->EmcPmacroObDdllLongDqRank0_4); |
| 324 | write32(®s->pmacro_ob_ddll_long_dq_rank0_5, |
| 325 | param->EmcPmacroObDdllLongDqRank0_5); |
| 326 | write32(®s->pmacro_ob_ddll_long_dq_rank1_0, |
| 327 | param->EmcPmacroObDdllLongDqRank1_0); |
| 328 | write32(®s->pmacro_ob_ddll_long_dq_rank1_1, |
| 329 | param->EmcPmacroObDdllLongDqRank1_1); |
| 330 | write32(®s->pmacro_ob_ddll_long_dq_rank1_2, |
| 331 | param->EmcPmacroObDdllLongDqRank1_2); |
| 332 | write32(®s->pmacro_ob_ddll_long_dq_rank1_3, |
| 333 | param->EmcPmacroObDdllLongDqRank1_3); |
| 334 | write32(®s->pmacro_ob_ddll_long_dq_rank1_4, |
| 335 | param->EmcPmacroObDdllLongDqRank1_4); |
| 336 | write32(®s->pmacro_ob_ddll_long_dq_rank1_5, |
| 337 | param->EmcPmacroObDdllLongDqRank1_5); |
| 338 | |
| 339 | write32(®s->pmacro_ob_ddll_long_dqs_rank0_0, |
| 340 | param->EmcPmacroObDdllLongDqsRank0_0); |
| 341 | write32(®s->pmacro_ob_ddll_long_dqs_rank0_1, |
| 342 | param->EmcPmacroObDdllLongDqsRank0_1); |
| 343 | write32(®s->pmacro_ob_ddll_long_dqs_rank0_2, |
| 344 | param->EmcPmacroObDdllLongDqsRank0_2); |
| 345 | write32(®s->pmacro_ob_ddll_long_dqs_rank0_3, |
| 346 | param->EmcPmacroObDdllLongDqsRank0_3); |
| 347 | write32(®s->pmacro_ob_ddll_long_dqs_rank0_4, |
| 348 | param->EmcPmacroObDdllLongDqsRank0_4); |
| 349 | write32(®s->pmacro_ob_ddll_long_dqs_rank0_5, |
| 350 | param->EmcPmacroObDdllLongDqsRank0_5); |
| 351 | write32(®s->pmacro_ob_ddll_long_dqs_rank1_0, |
| 352 | param->EmcPmacroObDdllLongDqsRank1_0); |
| 353 | write32(®s->pmacro_ob_ddll_long_dqs_rank1_1, |
| 354 | param->EmcPmacroObDdllLongDqsRank1_1); |
| 355 | write32(®s->pmacro_ob_ddll_long_dqs_rank1_2, |
| 356 | param->EmcPmacroObDdllLongDqsRank1_2); |
| 357 | write32(®s->pmacro_ob_ddll_long_dqs_rank1_3, |
| 358 | param->EmcPmacroObDdllLongDqsRank1_3); |
| 359 | write32(®s->pmacro_ob_ddll_long_dqs_rank1_4, |
| 360 | param->EmcPmacroObDdllLongDqsRank1_4); |
| 361 | write32(®s->pmacro_ob_ddll_long_dqs_rank1_5, |
| 362 | param->EmcPmacroObDdllLongDqsRank1_5); |
| 363 | write32(®s->pmacro_ib_ddll_long_dqs_rank0_0, |
| 364 | param->EmcPmacroIbDdllLongDqsRank0_0); |
| 365 | write32(®s->pmacro_ib_ddll_long_dqs_rank0_1, |
| 366 | param->EmcPmacroIbDdllLongDqsRank0_1); |
| 367 | write32(®s->pmacro_ib_ddll_long_dqs_rank0_2, |
| 368 | param->EmcPmacroIbDdllLongDqsRank0_2); |
| 369 | write32(®s->pmacro_ib_ddll_long_dqs_rank0_3, |
| 370 | param->EmcPmacroIbDdllLongDqsRank0_3); |
| 371 | write32(®s->pmacro_ib_ddll_long_dqs_rank1_0, |
| 372 | param->EmcPmacroIbDdllLongDqsRank1_0); |
| 373 | write32(®s->pmacro_ib_ddll_long_dqs_rank1_1, |
| 374 | param->EmcPmacroIbDdllLongDqsRank1_1); |
| 375 | write32(®s->pmacro_ib_ddll_long_dqs_rank1_2, |
| 376 | param->EmcPmacroIbDdllLongDqsRank1_2); |
| 377 | write32(®s->pmacro_ib_ddll_long_dqs_rank1_3, |
| 378 | param->EmcPmacroIbDdllLongDqsRank1_3); |
| 379 | write32(®s->pmacro_ddll_long_cmd_0, param->EmcPmacroDdllLongCmd_0); |
| 380 | write32(®s->pmacro_ddll_long_cmd_1, param->EmcPmacroDdllLongCmd_1); |
| 381 | write32(®s->pmacro_ddll_long_cmd_2, param->EmcPmacroDdllLongCmd_2); |
| 382 | write32(®s->pmacro_ddll_long_cmd_3, param->EmcPmacroDdllLongCmd_3); |
| 383 | write32(®s->pmacro_ddll_long_cmd_4, param->EmcPmacroDdllLongCmd_4); |
| 384 | write32(®s->pmacro_ddll_short_cmd_0, param->EmcPmacroDdllShortCmd_0); |
| 385 | write32(®s->pmacro_ddll_short_cmd_1, param->EmcPmacroDdllShortCmd_1); |
| 386 | write32(®s->pmacro_ddll_short_cmd_2, param->EmcPmacroDdllShortCmd_2); |
| 387 | write32(®s->pmacro_common_pad_tx_ctrl, cpm_step1); |
| 388 | } |
| 389 | |
| 390 | static void sdram_setup_wpr_carveouts(const struct sdram_params *param, |
| 391 | struct tegra_mc_regs *regs) |
| 392 | { |
| 393 | /* Program the 5 WPR carveouts with initial BCT settings. */ |
| 394 | write32(®s->security_carveout1_bom, |
| 395 | param->McGeneralizedCarveout1Bom); |
| 396 | write32(®s->security_carveout1_bom_hi, |
| 397 | param->McGeneralizedCarveout1BomHi); |
| 398 | write32(®s->security_carveout1_size_128kb, |
| 399 | param->McGeneralizedCarveout1Size128kb); |
| 400 | write32(®s->security_carveout1_ca0, |
| 401 | param->McGeneralizedCarveout1Access0); |
| 402 | write32(®s->security_carveout1_ca1, |
| 403 | param->McGeneralizedCarveout1Access1); |
| 404 | write32(®s->security_carveout1_ca2, |
| 405 | param->McGeneralizedCarveout1Access2); |
| 406 | write32(®s->security_carveout1_ca3, |
| 407 | param->McGeneralizedCarveout1Access3); |
| 408 | write32(®s->security_carveout1_ca4, |
| 409 | param->McGeneralizedCarveout1Access4); |
| 410 | write32(®s->security_carveout1_cfia0, |
| 411 | param->McGeneralizedCarveout1ForceInternalAccess0); |
| 412 | write32(®s->security_carveout1_cfia1, |
| 413 | param->McGeneralizedCarveout1ForceInternalAccess1); |
| 414 | write32(®s->security_carveout1_cfia2, |
| 415 | param->McGeneralizedCarveout1ForceInternalAccess2); |
| 416 | write32(®s->security_carveout1_cfia3, |
| 417 | param->McGeneralizedCarveout1ForceInternalAccess3); |
| 418 | write32(®s->security_carveout1_cfia4, |
| 419 | param->McGeneralizedCarveout1ForceInternalAccess4); |
| 420 | write32(®s->security_carveout1_cfg0, |
| 421 | param->McGeneralizedCarveout1Cfg0); |
| 422 | |
| 423 | write32(®s->security_carveout2_bom, |
| 424 | param->McGeneralizedCarveout2Bom); |
| 425 | write32(®s->security_carveout2_bom_hi, |
| 426 | param->McGeneralizedCarveout2BomHi); |
| 427 | write32(®s->security_carveout2_size_128kb, |
| 428 | param->McGeneralizedCarveout2Size128kb); |
| 429 | write32(®s->security_carveout2_ca0, |
| 430 | param->McGeneralizedCarveout2Access0); |
| 431 | write32(®s->security_carveout2_ca1, |
| 432 | param->McGeneralizedCarveout2Access1); |
| 433 | write32(®s->security_carveout2_ca2, |
| 434 | param->McGeneralizedCarveout2Access2); |
| 435 | write32(®s->security_carveout2_ca3, |
| 436 | param->McGeneralizedCarveout2Access3); |
| 437 | write32(®s->security_carveout2_ca4, |
| 438 | param->McGeneralizedCarveout2Access4); |
| 439 | write32(®s->security_carveout2_cfia0, |
| 440 | param->McGeneralizedCarveout2ForceInternalAccess0); |
| 441 | write32(®s->security_carveout2_cfia1, |
| 442 | param->McGeneralizedCarveout2ForceInternalAccess1); |
| 443 | write32(®s->security_carveout2_cfia2, |
| 444 | param->McGeneralizedCarveout2ForceInternalAccess2); |
| 445 | write32(®s->security_carveout2_cfia3, |
| 446 | param->McGeneralizedCarveout2ForceInternalAccess3); |
| 447 | write32(®s->security_carveout2_cfia4, |
| 448 | param->McGeneralizedCarveout2ForceInternalAccess4); |
| 449 | write32(®s->security_carveout2_cfg0, |
| 450 | param->McGeneralizedCarveout2Cfg0); |
| 451 | |
| 452 | write32(®s->security_carveout3_bom, |
| 453 | param->McGeneralizedCarveout3Bom); |
| 454 | write32(®s->security_carveout3_bom_hi, |
| 455 | param->McGeneralizedCarveout3BomHi); |
| 456 | write32(®s->security_carveout3_size_128kb, |
| 457 | param->McGeneralizedCarveout3Size128kb); |
| 458 | write32(®s->security_carveout3_ca0, |
| 459 | param->McGeneralizedCarveout3Access0); |
| 460 | write32(®s->security_carveout3_ca1, |
| 461 | param->McGeneralizedCarveout3Access1); |
| 462 | write32(®s->security_carveout3_ca2, |
| 463 | param->McGeneralizedCarveout3Access2); |
| 464 | write32(®s->security_carveout3_ca3, |
| 465 | param->McGeneralizedCarveout3Access3); |
| 466 | write32(®s->security_carveout3_ca4, |
| 467 | param->McGeneralizedCarveout3Access4); |
| 468 | write32(®s->security_carveout3_cfia0, |
| 469 | param->McGeneralizedCarveout3ForceInternalAccess0); |
| 470 | write32(®s->security_carveout3_cfia1, |
| 471 | param->McGeneralizedCarveout3ForceInternalAccess1); |
| 472 | write32(®s->security_carveout3_cfia2, |
| 473 | param->McGeneralizedCarveout3ForceInternalAccess2); |
| 474 | write32(®s->security_carveout3_cfia3, |
| 475 | param->McGeneralizedCarveout3ForceInternalAccess3); |
| 476 | write32(®s->security_carveout3_cfia4, |
| 477 | param->McGeneralizedCarveout3ForceInternalAccess4); |
| 478 | write32(®s->security_carveout3_cfg0, |
| 479 | param->McGeneralizedCarveout3Cfg0); |
| 480 | |
| 481 | write32(®s->security_carveout4_bom, |
| 482 | param->McGeneralizedCarveout4Bom); |
| 483 | write32(®s->security_carveout4_bom_hi, |
| 484 | param->McGeneralizedCarveout4BomHi); |
| 485 | write32(®s->security_carveout4_size_128kb, |
| 486 | param->McGeneralizedCarveout4Size128kb); |
| 487 | write32(®s->security_carveout4_ca0, |
| 488 | param->McGeneralizedCarveout4Access0); |
| 489 | write32(®s->security_carveout4_ca1, |
| 490 | param->McGeneralizedCarveout4Access1); |
| 491 | write32(®s->security_carveout4_ca2, |
| 492 | param->McGeneralizedCarveout4Access2); |
| 493 | write32(®s->security_carveout4_ca3, |
| 494 | param->McGeneralizedCarveout4Access3); |
| 495 | write32(®s->security_carveout4_ca4, |
| 496 | param->McGeneralizedCarveout4Access4); |
| 497 | write32(®s->security_carveout4_cfia0, |
| 498 | param->McGeneralizedCarveout4ForceInternalAccess0); |
| 499 | write32(®s->security_carveout4_cfia1, |
| 500 | param->McGeneralizedCarveout4ForceInternalAccess1); |
| 501 | write32(®s->security_carveout4_cfia2, |
| 502 | param->McGeneralizedCarveout4ForceInternalAccess2); |
| 503 | write32(®s->security_carveout4_cfia3, |
| 504 | param->McGeneralizedCarveout4ForceInternalAccess3); |
| 505 | write32(®s->security_carveout4_cfia4, |
| 506 | param->McGeneralizedCarveout4ForceInternalAccess4); |
| 507 | write32(®s->security_carveout4_cfg0, |
| 508 | param->McGeneralizedCarveout4Cfg0); |
| 509 | |
| 510 | write32(®s->security_carveout5_bom, |
| 511 | param->McGeneralizedCarveout5Bom); |
| 512 | write32(®s->security_carveout5_bom_hi, |
| 513 | param->McGeneralizedCarveout5BomHi); |
| 514 | write32(®s->security_carveout5_size_128kb, |
| 515 | param->McGeneralizedCarveout5Size128kb); |
| 516 | write32(®s->security_carveout5_ca0, |
| 517 | param->McGeneralizedCarveout5Access0); |
| 518 | write32(®s->security_carveout5_ca1, |
| 519 | param->McGeneralizedCarveout5Access1); |
| 520 | write32(®s->security_carveout5_ca2, |
| 521 | param->McGeneralizedCarveout5Access2); |
| 522 | write32(®s->security_carveout5_ca3, |
| 523 | param->McGeneralizedCarveout5Access3); |
| 524 | write32(®s->security_carveout5_ca4, |
| 525 | param->McGeneralizedCarveout5Access4); |
| 526 | write32(®s->security_carveout5_cfia0, |
| 527 | param->McGeneralizedCarveout5ForceInternalAccess0); |
| 528 | write32(®s->security_carveout5_cfia1, |
| 529 | param->McGeneralizedCarveout5ForceInternalAccess1); |
| 530 | write32(®s->security_carveout5_cfia2, |
| 531 | param->McGeneralizedCarveout5ForceInternalAccess2); |
| 532 | write32(®s->security_carveout5_cfia3, |
| 533 | param->McGeneralizedCarveout5ForceInternalAccess3); |
| 534 | write32(®s->security_carveout5_cfia4, |
| 535 | param->McGeneralizedCarveout5ForceInternalAccess4); |
| 536 | write32(®s->security_carveout5_cfg0, |
| 537 | param->McGeneralizedCarveout5Cfg0); |
| 538 | } |
| 539 | |
| 540 | static void sdram_init_mc(const struct sdram_params *param, |
| 541 | struct tegra_mc_regs *regs) |
| 542 | { |
| 543 | /* Initialize MC VPR settings */ |
| 544 | write32(®s->video_protect_bom, param->McVideoProtectBom); |
| 545 | write32(®s->video_protect_bom_adr_hi, |
| 546 | param->McVideoProtectBomAdrHi); |
| 547 | write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); |
| 548 | write32(®s->video_protect_vpr_override, |
| 549 | param->McVideoProtectVprOverride); |
| 550 | write32(®s->video_protect_vpr_override1, |
| 551 | param->McVideoProtectVprOverride1); |
| 552 | write32(®s->video_protect_gpu_override_0, |
| 553 | param->McVideoProtectGpuOverride0); |
| 554 | write32(®s->video_protect_gpu_override_1, |
| 555 | param->McVideoProtectGpuOverride1); |
| 556 | |
| 557 | /* Program SDRAM geometry paarameters */ |
| 558 | write32(®s->emem_adr_cfg, param->McEmemAdrCfg); |
| 559 | write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); |
| 560 | write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); |
| 561 | write32(®s->emem_adr_cfg_channel_mask, |
| 562 | param->McEmemAdrCfgChannelMask); |
| 563 | |
| 564 | /* Program bank swizzling */ |
| 565 | write32(®s->emem_adr_cfg_bank_mask_0, param->McEmemAdrCfgBankMask0); |
| 566 | write32(®s->emem_adr_cfg_bank_mask_1, param->McEmemAdrCfgBankMask1); |
| 567 | write32(®s->emem_adr_cfg_bank_mask_2, param->McEmemAdrCfgBankMask2); |
| 568 | |
| 569 | /* Program external memory aperature (base and size) */ |
| 570 | write32(®s->emem_cfg, param->McEmemCfg); |
| 571 | |
| 572 | /* Program SEC carveout (base and size) */ |
| 573 | write32(®s->sec_carveout_bom, param->McSecCarveoutBom); |
| 574 | write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); |
| 575 | write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); |
| 576 | |
| 577 | /* Program MTS carveout (base and size) */ |
| 578 | write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); |
| 579 | write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); |
| 580 | write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); |
| 581 | |
| 582 | /* Initialize the WPR carveouts */ |
| 583 | sdram_setup_wpr_carveouts(param, regs); |
| 584 | |
| 585 | /* Program the memory arbiter */ |
| 586 | write32(®s->emem_arb_cfg, param->McEmemArbCfg); |
| 587 | write32(®s->emem_arb_outstanding_req, |
| 588 | param->McEmemArbOutstandingReq); |
| 589 | write32(®s->emem_arb_refpb_hp_ctrl, param->McEmemArbRefpbHpCtrl); |
| 590 | write32(®s->emem_arb_refpb_bank_ctrl, param->McEmemArbRefpbBankCtrl); |
| 591 | write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); |
| 592 | write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); |
| 593 | write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); |
| 594 | write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); |
| 595 | write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); |
| 596 | write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); |
| 597 | write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); |
| 598 | write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); |
| 599 | write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); |
| 600 | write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); |
| 601 | write32(®s->emem_arb_timing_ccdmw, param->McEmemArbTimingCcdmw); |
| 602 | write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); |
| 603 | write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); |
| 604 | write32(®s->emem_arb_timing_rfcpb, param->McEmemArbTimingRFCPB); |
| 605 | write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); |
| 606 | write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); |
| 607 | write32(®s->emem_arb_misc0, param->McEmemArbMisc0); |
| 608 | write32(®s->emem_arb_misc1, param->McEmemArbMisc1); |
| 609 | write32(®s->emem_arb_misc2, param->McEmemArbMisc2); |
| 610 | write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); |
| 611 | write32(®s->emem_arb_override, param->McEmemArbOverride); |
| 612 | write32(®s->emem_arb_override_1, param->McEmemArbOverride1); |
| 613 | write32(®s->emem_arb_rsv, param->McEmemArbRsv); |
| 614 | write32(®s->da_config0, param->McDaCfg0); |
| 615 | |
| 616 | /* Trigger MC timing update */ |
| 617 | write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); |
| 618 | |
| 619 | /* Program second-level clock enable overrides */ |
| 620 | write32(®s->clken_override, param->McClkenOverride); |
| 621 | |
| 622 | /* Program statistics gathering */ |
| 623 | write32(®s->stat_control, param->McStatControl); |
| 624 | } |
| 625 | |
| 626 | static void sdram_init_emc(const struct sdram_params *param, |
| 627 | struct tegra_emc_regs *regs) |
| 628 | { |
| 629 | /* Program SDRAM geometry parameters */ |
| 630 | write32(®s->adr_cfg, param->EmcAdrCfg); |
| 631 | |
| 632 | /* Program second-level clock enable overrides */ |
| 633 | write32(®s->clken_override, param->EmcClkenOverride); |
| 634 | |
| 635 | /* Program EMC pad auto calibration */ |
| 636 | write32(®s->pmacro_autocal_cfg0, param->EmcPmacroAutocalCfg0); |
| 637 | write32(®s->pmacro_autocal_cfg1, param->EmcPmacroAutocalCfg1); |
| 638 | write32(®s->pmacro_autocal_cfg2, param->EmcPmacroAutocalCfg2); |
| 639 | |
| 640 | write32(®s->auto_cal_vref_sel0, param->EmcAutoCalVrefSel0); |
| 641 | write32(®s->auto_cal_vref_sel1, param->EmcAutoCalVrefSel1); |
| 642 | |
| 643 | write32(®s->auto_cal_interval, param->EmcAutoCalInterval); |
| 644 | write32(®s->auto_cal_config, param->EmcAutoCalConfig); |
| 645 | udelay(param->EmcAutoCalWait); |
| 646 | } |
| 647 | |
| 648 | static void sdram_set_emc_timing(const struct sdram_params *param, |
| 649 | struct tegra_emc_regs *regs) |
| 650 | { |
| 651 | /* Program EMC timing configuration */ |
| 652 | write32(®s->cfg_2, param->EmcCfg2); |
| 653 | write32(®s->cfg_pipe, param->EmcCfgPipe); |
| 654 | write32(®s->cfg_pipe1, param->EmcCfgPipe1); |
| 655 | write32(®s->cfg_pipe2, param->EmcCfgPipe2); |
| 656 | write32(®s->cmdq, param->EmcCmdQ); |
| 657 | write32(®s->mc2emcq, param->EmcMc2EmcQ); |
| 658 | write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); |
| 659 | write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); |
| 660 | write32(®s->fbio_cfg5, param->EmcFbioCfg5); |
| 661 | write32(®s->rc, param->EmcRc); |
| 662 | write32(®s->rfc, param->EmcRfc); |
| 663 | write32(®s->rfcpb, param->EmcRfcPb); |
| 664 | write32(®s->refctrl2, param->EmcRefctrl2); |
| 665 | write32(®s->rfc_slr, param->EmcRfcSlr); |
| 666 | write32(®s->ras, param->EmcRas); |
| 667 | write32(®s->rp, param->EmcRp); |
| 668 | write32(®s->tppd, param->EmcTppd); |
| 669 | write32(®s->r2r, param->EmcR2r); |
| 670 | write32(®s->w2w, param->EmcW2w); |
| 671 | write32(®s->r2w, param->EmcR2w); |
| 672 | write32(®s->w2r, param->EmcW2r); |
| 673 | write32(®s->r2p, param->EmcR2p); |
| 674 | write32(®s->w2p, param->EmcW2p); |
| 675 | write32(®s->ccdmw, param->EmcCcdmw); |
| 676 | write32(®s->rd_rcd, param->EmcRdRcd); |
| 677 | write32(®s->wr_rcd, param->EmcWrRcd); |
| 678 | write32(®s->rrd, param->EmcRrd); |
| 679 | write32(®s->rext, param->EmcRext); |
| 680 | write32(®s->wext, param->EmcWext); |
| 681 | write32(®s->wdv, param->EmcWdv); |
| 682 | write32(®s->wdv_chk, param->EmcWdvChk); |
| 683 | write32(®s->wsv, param->EmcWsv); |
| 684 | write32(®s->wev, param->EmcWev); |
| 685 | write32(®s->wdv_mask, param->EmcWdvMask); |
| 686 | write32(®s->ws_duration, param->EmcWsDuration); |
| 687 | write32(®s->we_duration, param->EmcWeDuration); |
| 688 | write32(®s->quse, param->EmcQUse); |
| 689 | write32(®s->quse_width, param->EmcQuseWidth); |
| 690 | write32(®s->ibdly, param->EmcIbdly); |
| 691 | write32(®s->obdly, param->EmcObdly); |
| 692 | write32(®s->einput, param->EmcEInput); |
| 693 | write32(®s->einput_duration, param->EmcEInputDuration); |
| 694 | write32(®s->puterm_extra, param->EmcPutermExtra); |
| 695 | write32(®s->puterm_width, param->EmcPutermWidth); |
| 696 | |
| 697 | write32(®s->pmacro_common_pad_tx_ctrl, |
| 698 | param->EmcPmacroCommonPadTxCtrl); |
| 699 | write32(®s->dbg, param->EmcDbg); |
| 700 | write32(®s->qrst, param->EmcQRst); |
| 701 | write32(®s->issue_qrst, 1); |
| 702 | write32(®s->issue_qrst, 0); |
| 703 | write32(®s->qsafe, param->EmcQSafe); |
| 704 | write32(®s->rdv, param->EmcRdv); |
| 705 | write32(®s->rdv_mask, param->EmcRdvMask); |
| 706 | write32(®s->rdv_early, param->EmcRdvEarly); |
| 707 | write32(®s->rdv_early_mask, param->EmcRdvEarlyMask); |
| 708 | write32(®s->qpop, param->EmcQpop); |
| 709 | write32(®s->refresh, param->EmcRefresh); |
| 710 | write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); |
| 711 | write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); |
| 712 | write32(®s->pdex2wr, param->EmcPdEx2Wr); |
| 713 | write32(®s->pdex2rd, param->EmcPdEx2Rd); |
| 714 | write32(®s->pchg2pden, param->EmcPChg2Pden); |
| 715 | write32(®s->act2pden, param->EmcAct2Pden); |
| 716 | write32(®s->ar2pden, param->EmcAr2Pden); |
| 717 | write32(®s->rw2pden, param->EmcRw2Pden); |
| 718 | write32(®s->cke2pden, param->EmcCke2Pden); |
| 719 | write32(®s->pdex2cke, param->EmcPdex2Cke); |
| 720 | write32(®s->pdex2mrr, param->EmcPdex2Mrr); |
| 721 | write32(®s->txsr, param->EmcTxsr); |
| 722 | write32(®s->txsrdll, param->EmcTxsrDll); |
| 723 | write32(®s->tcke, param->EmcTcke); |
| 724 | write32(®s->tckesr, param->EmcTckesr); |
| 725 | write32(®s->tpd, param->EmcTpd); |
| 726 | write32(®s->tfaw, param->EmcTfaw); |
| 727 | write32(®s->trpab, param->EmcTrpab); |
| 728 | write32(®s->tclkstable, param->EmcTClkStable); |
| 729 | write32(®s->tclkstop, param->EmcTClkStop); |
| 730 | write32(®s->trefbw, param->EmcTRefBw); |
| 731 | write32(®s->odt_write, param->EmcOdtWrite); |
| 732 | write32(®s->cfg_dig_dll, param->EmcCfgDigDll); |
| 733 | write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); |
| 734 | |
| 735 | /* Don't write CFG_ADR_EN (bit 1) here - lock bit written later */ |
| 736 | write32(®s->fbio_spare, param->EmcFbioSpare & ~CFG_ADR_EN_LOCKED); |
| 737 | write32(®s->cfg_rsv, param->EmcCfgRsv); |
| 738 | write32(®s->pmc_scratch1, param->EmcPmcScratch1); |
| 739 | write32(®s->pmc_scratch2, param->EmcPmcScratch2); |
| 740 | write32(®s->pmc_scratch3, param->EmcPmcScratch3); |
| 741 | write32(®s->acpd_control, param->EmcAcpdControl); |
| 742 | write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); |
| 743 | |
| 744 | /* |
| 745 | * Set pipe bypass enable bits before sending any DRAM commands. |
| 746 | * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured. |
| 747 | */ |
| 748 | writebits(param->EmcCfg, ®s->cfg, |
| 749 | (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK | |
| 750 | EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK | |
| 751 | EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK)); |
| 752 | } |
| 753 | |
| 754 | static void sdram_patch_bootrom(const struct sdram_params *param, |
| 755 | struct tegra_mc_regs *regs) |
| 756 | { |
| 757 | if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) { |
| 758 | uintptr_t addr = ((param->BootRomPatchControl & |
| 759 | BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> |
| 760 | BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); |
| 761 | addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); |
| 762 | write32((uint32_t *)addr, param->BootRomPatchData); |
| 763 | write32(®s->timing_control, |
| 764 | EMC_TIMING_CONTROL_TIMING_UPDATE); |
| 765 | } |
| 766 | } |
| 767 | |
| 768 | static void sdram_rel_dpd(const struct sdram_params *param, |
| 769 | struct tegra_pmc_regs *regs) |
| 770 | { |
| 771 | u32 dpd3_val, dpd3_val_sel_dpd; |
| 772 | |
| 773 | /* Release SEL_DPD_CMD */ |
| 774 | dpd3_val = (param->EmcPmcScratch1 & 0x3FFFFFFF) | DPD_OFF; |
| 775 | dpd3_val_sel_dpd = dpd3_val & 0xCFFF0000; |
| 776 | write32(®s->io_dpd3_req, dpd3_val_sel_dpd); |
| 777 | udelay(param->PmcIoDpd3ReqWait); |
| 778 | } |
| 779 | |
| 780 | /* Program DPD3/DPD4 regs (coldboot path) */ |
| 781 | static void sdram_set_dpd(const struct sdram_params *param, |
| 782 | struct tegra_pmc_regs *regs) |
| 783 | { |
| 784 | u32 dpd3_val, dpd3_val_sel_dpd; |
| 785 | u32 dpd4_val, dpd4_val_e_dpd, dpd4_val_e_dpd_vttgen; |
| 786 | |
| 787 | /* Enable sel_dpd on unused pins */ |
| 788 | dpd3_val = (param->EmcPmcScratch1 & 0x3FFFFFFF) | DPD_ON; |
| 789 | dpd3_val_sel_dpd = (dpd3_val ^ 0x0000FFFF) & 0xC000FFFF; |
| 790 | write32(®s->io_dpd3_req, dpd3_val_sel_dpd); |
| 791 | udelay(param->PmcIoDpd3ReqWait); |
| 792 | |
| 793 | dpd4_val = dpd3_val; |
| 794 | /* Disable e_dpd_vttgen */ |
| 795 | dpd4_val_e_dpd_vttgen = (dpd4_val ^ 0x3FFF0000) & 0xFFFF0000; |
| 796 | write32(®s->io_dpd4_req, dpd4_val_e_dpd_vttgen); |
| 797 | udelay(param->PmcIoDpd4ReqWait); |
| 798 | |
| 799 | /* Disable e_dpd_bg */ |
| 800 | dpd4_val_e_dpd = (dpd4_val ^ 0x0000FFFF) & 0xC000FFFF; |
| 801 | write32(®s->io_dpd4_req, dpd4_val_e_dpd); |
| 802 | udelay(param->PmcIoDpd4ReqWait); |
| 803 | |
| 804 | write32(®s->weak_bias, 0); |
| 805 | /* Add a wait to make sure clock switch takes place */ |
| 806 | udelay(1); |
| 807 | } |
| 808 | |
| 809 | static void sdram_set_clock_enable_signal(const struct sdram_params *param, |
| 810 | struct tegra_emc_regs *regs) |
| 811 | { |
| 812 | volatile uint32_t dummy = 0; |
| 813 | uint32_t val = 0; |
| 814 | |
| 815 | if (param->MemoryType == NvBootMemoryType_LpDdr4) { |
| 816 | |
| 817 | val = (param->EmcPinGpioEn << EMC_PIN_GPIOEN_SHIFT) | |
| 818 | (param->EmcPinGpio << EMC_PIN_GPIO_SHIFT); |
| 819 | write32(®s->pin, val); |
| 820 | |
| 821 | clrbits_le32(®s->pin, |
| 822 | (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | |
| 823 | EMC_PIN_CKE_MASK)); |
| 824 | /* |
| 825 | * Assert dummy read of PIN register to ensure above write goes |
| 826 | * through. Wait an additional 200us here as per NVIDIA. |
| 827 | */ |
| 828 | dummy |= read32(®s->pin); |
| 829 | udelay(param->EmcPinExtraWait + 200); |
| 830 | |
| 831 | /* Deassert reset */ |
| 832 | setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE); |
| 833 | |
| 834 | /* |
| 835 | * Assert dummy read of PIN register to ensure above write goes |
| 836 | * through. Wait an additional 2000us here as per NVIDIA. |
| 837 | */ |
| 838 | dummy |= read32(®s->pin); |
| 839 | udelay(param->EmcPinExtraWait + 2000); |
| 840 | } |
| 841 | |
| 842 | /* Enable clock enable signal */ |
| 843 | setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL); |
| 844 | |
| 845 | /* Dummy read of PIN register to ensure final write goes through */ |
| 846 | dummy |= read32(®s->pin); |
| 847 | udelay(param->EmcPinProgramWait); |
| 848 | |
| 849 | if (!dummy) |
| 850 | die("Failed to program EMC pin."); |
| 851 | |
| 852 | if (param->MemoryType != NvBootMemoryType_LpDdr4) { |
| 853 | |
| 854 | /* Send NOP (trigger just needs to be non-zero) */ |
| 855 | writebits(((1 << EMC_NOP_CMD_SHIFT) | |
| 856 | (param->EmcDevSelect << EMC_NOP_DEV_SELECTN_SHIFT)), |
| 857 | ®s->nop, |
| 858 | EMC_NOP_CMD_MASK | EMC_NOP_DEV_SELECTN_MASK); |
| 859 | } |
| 860 | |
| 861 | /* On coldboot w/LPDDR2/3, wait 200 uSec after asserting CKE high */ |
| 862 | if (param->MemoryType == NvBootMemoryType_LpDdr2) |
| 863 | udelay(param->EmcPinExtraWait + 200); |
| 864 | } |
| 865 | |
| 866 | static void sdram_init_lpddr3(const struct sdram_params *param, |
| 867 | struct tegra_emc_regs *regs) |
| 868 | { |
| 869 | /* Precharge all banks. DEV_SELECTN = 0 => Select all devices */ |
| 870 | write32(®s->pre, |
| 871 | ((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1)); |
| 872 | |
| 873 | /* Send Reset MRW command */ |
| 874 | write32(®s->mrw, param->EmcMrwResetCommand); |
| 875 | udelay(param->EmcMrwResetNInitWait); |
| 876 | |
| 877 | write32(®s->mrw, param->EmcZcalInitDev0); |
| 878 | udelay(param->EmcZcalInitWait); |
| 879 | |
| 880 | if ((param->EmcDevSelect & 2) == 0) { |
| 881 | write32(®s->mrw, param->EmcZcalInitDev1); |
| 882 | udelay(param->EmcZcalInitWait); |
| 883 | } |
| 884 | |
| 885 | /* Write mode registers */ |
| 886 | write32(®s->mrw2, param->EmcMrw2); |
| 887 | write32(®s->mrw, param->EmcMrw1); |
| 888 | write32(®s->mrw3, param->EmcMrw3); |
| 889 | write32(®s->mrw4, param->EmcMrw4); |
| 890 | |
| 891 | /* Patch 6 using BCT spare variables */ |
| 892 | sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11); |
| 893 | |
| 894 | if (param->EmcExtraModeRegWriteEnable) |
| 895 | write32(®s->mrw, param->EmcMrwExtra); |
| 896 | } |
| 897 | |
| 898 | static void sdram_init_lpddr4(const struct sdram_params *param, |
| 899 | struct tegra_emc_regs *regs) |
| 900 | { |
| 901 | /* Patch 6 using BCT spare variables */ |
| 902 | sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11); |
| 903 | |
| 904 | /* Write mode registers */ |
| 905 | write32(®s->mrw2, param->EmcMrw2); |
| 906 | write32(®s->mrw, param->EmcMrw1); |
| 907 | write32(®s->mrw3, param->EmcMrw3); |
| 908 | write32(®s->mrw4, param->EmcMrw4); |
| 909 | write32(®s->mrw6, param->EmcMrw6); |
| 910 | write32(®s->mrw14, param->EmcMrw14); |
| 911 | |
| 912 | write32(®s->mrw8, param->EmcMrw8); |
| 913 | write32(®s->mrw12, param->EmcMrw12); |
| 914 | write32(®s->mrw9, param->EmcMrw9); |
| 915 | write32(®s->mrw13, param->EmcMrw13); |
| 916 | |
| 917 | /* Issue ZQCAL start, device 0 */ |
| 918 | write32(®s->zq_cal, param->EmcZcalInitDev0); |
| 919 | udelay(param->EmcZcalInitWait); |
| 920 | /* Issue ZQCAL latch */ |
| 921 | write32(®s->zq_cal, (param->EmcZcalInitDev0 ^ 0x3)); |
| 922 | |
| 923 | if ((param->EmcDevSelect & 2) == 0) { |
| 924 | /* Same for device 1 */ |
| 925 | write32(®s->zq_cal, param->EmcZcalInitDev1); |
| 926 | udelay(param->EmcZcalInitWait); |
| 927 | write32(®s->zq_cal, (param->EmcZcalInitDev1 ^ 0x3)); |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | static void sdram_init_zq_calibration(const struct sdram_params *param, |
| 932 | struct tegra_emc_regs *regs) |
| 933 | { |
| 934 | if (param->MemoryType == NvBootMemoryType_LpDdr2) |
| 935 | sdram_init_lpddr3(param, regs); |
| 936 | else if (param->MemoryType == NvBootMemoryType_LpDdr4) |
| 937 | sdram_init_lpddr4(param, regs); |
| 938 | } |
| 939 | |
| 940 | static void sdram_set_zq_calibration(const struct sdram_params *param, |
| 941 | struct tegra_emc_regs *regs) |
| 942 | { |
| 943 | if (param->EmcAutoCalInterval == 0) |
| 944 | write32(®s->auto_cal_config, |
| 945 | param->EmcAutoCalConfig | AUTOCAL_MEASURE_STALL_ENABLE); |
| 946 | |
| 947 | write32(®s->pmacro_brick_ctrl_rfu2, param->EmcPmacroBrickCtrlRfu2); |
| 948 | |
| 949 | /* ZQ CAL setup (not actually issuing ZQ CAL now) */ |
| 950 | if (param->MemoryType == NvBootMemoryType_LpDdr4) { |
| 951 | write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); |
| 952 | write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); |
| 953 | } |
| 954 | |
| 955 | sdram_trigger_emc_timing_update(regs); |
| 956 | udelay(param->EmcTimingControlWait); |
| 957 | } |
| 958 | |
| 959 | static void sdram_set_refresh(const struct sdram_params *param, |
| 960 | struct tegra_emc_regs *regs) |
| 961 | { |
| 962 | /* Insert burst refresh */ |
| 963 | if (param->EmcExtraRefreshNum > 0) { |
| 964 | uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1; |
| 965 | |
| 966 | writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED | |
| 967 | (refresh_num << EMC_REF_NUM_SHIFT) | |
| 968 | (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)), |
| 969 | ®s->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK | |
| 970 | EMC_REF_NUM_MASK | |
| 971 | EMC_REF_DEV_SELECTN_MASK)); |
| 972 | } |
| 973 | |
| 974 | /* Enable refresh */ |
| 975 | write32(®s->refctrl, |
| 976 | (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); |
| 977 | |
| 978 | /* |
| 979 | * NOTE: Programming CFG must happen after REFCTRL to delay |
| 980 | * active power-down to after init (DDR2 constraint). |
| 981 | */ |
| 982 | write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); |
| 983 | write32(®s->cfg_update, param->EmcCfgUpdate); |
| 984 | write32(®s->cfg, param->EmcCfg); |
| 985 | write32(®s->fdpd_ctrl_dq, param->EmcFdpdCtrlDq); |
| 986 | write32(®s->fdpd_ctrl_cmd, param->EmcFdpdCtrlCmd); |
| 987 | write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); |
| 988 | |
| 989 | /* Write addr swizzle lock bit */ |
| 990 | write32(®s->fbio_spare, param->EmcFbioSpare | CFG_ADR_EN_LOCKED); |
| 991 | |
| 992 | /* Re-trigger timing to latch power saving functions */ |
| 993 | sdram_trigger_emc_timing_update(regs); |
| 994 | |
| 995 | /* Enable EMC pipe clock gating */ |
| 996 | write32(®s->cfg_pipe_clk, param->EmcCfgPipeClk); |
| 997 | /* Depending on freqency, enable CMD/CLK fdpd */ |
| 998 | write32(®s->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp); |
| 999 | } |
| 1000 | |
| 1001 | #define AHB_ARB_XBAR_CTRL 0x6000C0E0 |
| 1002 | |
| 1003 | static void sdram_enable_arbiter(const struct sdram_params *param) |
| 1004 | { |
| 1005 | /* TODO(hungte) Move values here to standalone header file. */ |
| 1006 | uint32_t *ahb_arbitration_xbar_ctrl = (uint32_t *)(AHB_ARB_XBAR_CTRL); |
| 1007 | |
| 1008 | setbits_le32(ahb_arbitration_xbar_ctrl, |
| 1009 | param->AhbArbitrationXbarCtrlMemInitDone << 16); |
| 1010 | } |
| 1011 | |
| 1012 | static void sdram_lock_carveouts(const struct sdram_params *param, |
| 1013 | struct tegra_mc_regs *regs) |
| 1014 | { |
| 1015 | /* Lock carveouts, and emem_cfg registers */ |
| 1016 | write32(®s->video_protect_reg_ctrl, |
| 1017 | param->McVideoProtectWriteAccess); |
| 1018 | write32(®s->sec_carveout_reg_ctrl, |
| 1019 | param->McSecCarveoutProtectWriteAccess); |
| 1020 | write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); |
| 1021 | |
| 1022 | /* Write this last, locks access */ |
| 1023 | write32(®s->emem_cfg_access_ctrl, |
| 1024 | MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); |
| 1025 | } |
| 1026 | |
| 1027 | void sdram_init(const struct sdram_params *param) |
| 1028 | { |
| 1029 | struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)TEGRA_PMC_BASE; |
| 1030 | struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; |
| 1031 | struct tegra_emc_regs *emc = (struct tegra_emc_regs *)TEGRA_EMC_BASE; |
| 1032 | |
| 1033 | printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n", |
| 1034 | param->MemoryType, clock_get_pll_input_khz() * |
| 1035 | param->PllMFeedbackDivider / param->PllMInputDivider / |
| 1036 | (1 + param->PllMPostDivider)); |
| 1037 | if (param->MemoryType != NvBootMemoryType_LpDdr4 && |
| 1038 | param->MemoryType != NvBootMemoryType_LpDdr2) |
| 1039 | die("Unsupported memory type!\n"); |
| 1040 | |
| 1041 | sdram_configure_pmc(param, pmc); |
| 1042 | sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); |
| 1043 | |
| 1044 | sdram_set_dpd(param, pmc); |
| 1045 | sdram_start_clocks(param, emc); |
| 1046 | sdram_set_pad_macros(param, emc); |
| 1047 | sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5); |
| 1048 | |
| 1049 | sdram_trigger_emc_timing_update(emc); |
| 1050 | sdram_init_mc(param, mc); |
| 1051 | sdram_init_emc(param, emc); |
| 1052 | sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9); |
| 1053 | |
| 1054 | sdram_set_emc_timing(param, emc); |
| 1055 | sdram_patch_bootrom(param, mc); |
| 1056 | sdram_rel_dpd(param, pmc); |
| 1057 | sdram_set_zq_calibration(param, emc); |
| 1058 | sdram_set_ddr_control(param, pmc); |
| 1059 | sdram_set_clock_enable_signal(param, emc); |
| 1060 | |
| 1061 | sdram_init_zq_calibration(param, emc); |
| 1062 | |
| 1063 | /* Set package and DPD pad control */ |
| 1064 | write32(&pmc->ddr_cfg, param->PmcDdrCfg); |
| 1065 | |
| 1066 | /* Start periodic ZQ calibration (LPDDRx only) */ |
| 1067 | if (param->MemoryType == NvBootMemoryType_LpDdr4 || |
| 1068 | param->MemoryType == NvBootMemoryType_LpDdr2) { |
| 1069 | write32(&emc->zcal_interval, param->EmcZcalInterval); |
| 1070 | write32(&emc->zcal_wait_cnt, param->EmcZcalWaitCnt); |
| 1071 | write32(&emc->zcal_mrw_cmd, param->EmcZcalMrwCmd); |
| 1072 | } |
| 1073 | sdram_patch(param->EmcBctSpare12, param->EmcBctSpare13); |
| 1074 | |
| 1075 | sdram_trigger_emc_timing_update(emc); |
| 1076 | sdram_set_refresh(param, emc); |
| 1077 | sdram_enable_arbiter(param); |
| 1078 | sdram_lock_carveouts(param, mc); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1079 | } |