Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * Copyright (C) 2013 Vladimir Serbinenko |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <string.h> |
| 24 | #include <device/pci_ops.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 25 | #include <drivers/intel/gma/edid.h> |
| 26 | #include <drivers/intel/gma/i915.h> |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 27 | #include <drivers/intel/gma/intel_bios.h> |
Nico Huber | 1822816 | 2017-06-08 16:31:57 +0200 | [diff] [blame] | 28 | #include <drivers/intel/gma/libgfxinit.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 29 | #include <pc80/vga.h> |
| 30 | #include <pc80/vga_io.h> |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 31 | #include <southbridge/intel/ibexpeak/nvs.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 32 | #include <drivers/intel/gma/opregion.h> |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 33 | #include <cbmem.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 34 | |
| 35 | #include "chip.h" |
| 36 | #include "nehalem.h" |
| 37 | |
| 38 | struct gt_powermeter { |
| 39 | u16 reg; |
| 40 | u32 value; |
| 41 | }; |
| 42 | |
| 43 | static const struct gt_powermeter snb_pm_gt1[] = { |
| 44 | {0xa200, 0xcc000000}, |
| 45 | {0xa204, 0x07000040}, |
| 46 | {0xa208, 0x0000fe00}, |
| 47 | {0xa20c, 0x00000000}, |
| 48 | {0xa210, 0x17000000}, |
| 49 | {0xa214, 0x00000021}, |
| 50 | {0xa218, 0x0817fe19}, |
| 51 | {0xa21c, 0x00000000}, |
| 52 | {0xa220, 0x00000000}, |
| 53 | {0xa224, 0xcc000000}, |
| 54 | {0xa228, 0x07000040}, |
| 55 | {0xa22c, 0x0000fe00}, |
| 56 | {0xa230, 0x00000000}, |
| 57 | {0xa234, 0x17000000}, |
| 58 | {0xa238, 0x00000021}, |
| 59 | {0xa23c, 0x0817fe19}, |
| 60 | {0xa240, 0x00000000}, |
| 61 | {0xa244, 0x00000000}, |
| 62 | {0xa248, 0x8000421e}, |
| 63 | {0} |
| 64 | }; |
| 65 | |
| 66 | static const struct gt_powermeter snb_pm_gt2[] = { |
| 67 | {0xa200, 0x330000a6}, |
| 68 | {0xa204, 0x402d0031}, |
| 69 | {0xa208, 0x00165f83}, |
| 70 | {0xa20c, 0xf1000000}, |
| 71 | {0xa210, 0x00000000}, |
| 72 | {0xa214, 0x00160016}, |
| 73 | {0xa218, 0x002a002b}, |
| 74 | {0xa21c, 0x00000000}, |
| 75 | {0xa220, 0x00000000}, |
| 76 | {0xa224, 0x330000a6}, |
| 77 | {0xa228, 0x402d0031}, |
| 78 | {0xa22c, 0x00165f83}, |
| 79 | {0xa230, 0xf1000000}, |
| 80 | {0xa234, 0x00000000}, |
| 81 | {0xa238, 0x00160016}, |
| 82 | {0xa23c, 0x002a002b}, |
| 83 | {0xa240, 0x00000000}, |
| 84 | {0xa244, 0x00000000}, |
| 85 | {0xa248, 0x8000421e}, |
| 86 | {0} |
| 87 | }; |
| 88 | |
| 89 | static const struct gt_powermeter ivb_pm_gt1[] = { |
| 90 | {0xa800, 0x00000000}, |
| 91 | {0xa804, 0x00021c00}, |
| 92 | {0xa808, 0x00000403}, |
| 93 | {0xa80c, 0x02001700}, |
| 94 | {0xa810, 0x05000200}, |
| 95 | {0xa814, 0x00000000}, |
| 96 | {0xa818, 0x00690500}, |
| 97 | {0xa81c, 0x0000007f}, |
| 98 | {0xa820, 0x01002501}, |
| 99 | {0xa824, 0x00000300}, |
| 100 | {0xa828, 0x01000331}, |
| 101 | {0xa82c, 0x0000000c}, |
| 102 | {0xa830, 0x00010016}, |
| 103 | {0xa834, 0x01100101}, |
| 104 | {0xa838, 0x00010103}, |
| 105 | {0xa83c, 0x00041300}, |
| 106 | {0xa840, 0x00000b30}, |
| 107 | {0xa844, 0x00000000}, |
| 108 | {0xa848, 0x7f000000}, |
| 109 | {0xa84c, 0x05000008}, |
| 110 | {0xa850, 0x00000001}, |
| 111 | {0xa854, 0x00000004}, |
| 112 | {0xa858, 0x00000007}, |
| 113 | {0xa85c, 0x00000000}, |
| 114 | {0xa860, 0x00010000}, |
| 115 | {0xa248, 0x0000221e}, |
| 116 | {0xa900, 0x00000000}, |
| 117 | {0xa904, 0x00001c00}, |
| 118 | {0xa908, 0x00000000}, |
| 119 | {0xa90c, 0x06000000}, |
| 120 | {0xa910, 0x09000200}, |
| 121 | {0xa914, 0x00000000}, |
| 122 | {0xa918, 0x00590000}, |
| 123 | {0xa91c, 0x00000000}, |
| 124 | {0xa920, 0x04002501}, |
| 125 | {0xa924, 0x00000100}, |
| 126 | {0xa928, 0x03000410}, |
| 127 | {0xa92c, 0x00000000}, |
| 128 | {0xa930, 0x00020000}, |
| 129 | {0xa934, 0x02070106}, |
| 130 | {0xa938, 0x00010100}, |
| 131 | {0xa93c, 0x00401c00}, |
| 132 | {0xa940, 0x00000000}, |
| 133 | {0xa944, 0x00000000}, |
| 134 | {0xa948, 0x10000e00}, |
| 135 | {0xa94c, 0x02000004}, |
| 136 | {0xa950, 0x00000001}, |
| 137 | {0xa954, 0x00000004}, |
| 138 | {0xa960, 0x00060000}, |
| 139 | {0xaa3c, 0x00001c00}, |
| 140 | {0xaa54, 0x00000004}, |
| 141 | {0xaa60, 0x00060000}, |
| 142 | {0} |
| 143 | }; |
| 144 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 145 | static const struct gt_powermeter ivb_pm_gt2_17w[] = { |
| 146 | {0xa800, 0x20000000}, |
| 147 | {0xa804, 0x000e3800}, |
| 148 | {0xa808, 0x00000806}, |
| 149 | {0xa80c, 0x0c002f00}, |
| 150 | {0xa810, 0x0c000800}, |
| 151 | {0xa814, 0x00000000}, |
| 152 | {0xa818, 0x00d20d00}, |
| 153 | {0xa81c, 0x000000ff}, |
| 154 | {0xa820, 0x03004b02}, |
| 155 | {0xa824, 0x00000600}, |
| 156 | {0xa828, 0x07000773}, |
| 157 | {0xa82c, 0x00000000}, |
| 158 | {0xa830, 0x00020032}, |
| 159 | {0xa834, 0x1520040d}, |
| 160 | {0xa838, 0x00020105}, |
| 161 | {0xa83c, 0x00083700}, |
| 162 | {0xa840, 0x000016ff}, |
| 163 | {0xa844, 0x00000000}, |
| 164 | {0xa848, 0xff000000}, |
| 165 | {0xa84c, 0x0a000010}, |
| 166 | {0xa850, 0x00000002}, |
| 167 | {0xa854, 0x00000008}, |
| 168 | {0xa858, 0x0000000f}, |
| 169 | {0xa85c, 0x00000000}, |
| 170 | {0xa860, 0x00020000}, |
| 171 | {0xa248, 0x0000221e}, |
| 172 | {0xa900, 0x00000000}, |
| 173 | {0xa904, 0x00003800}, |
| 174 | {0xa908, 0x00000000}, |
| 175 | {0xa90c, 0x0c000000}, |
| 176 | {0xa910, 0x12000800}, |
| 177 | {0xa914, 0x00000000}, |
| 178 | {0xa918, 0x00b20000}, |
| 179 | {0xa91c, 0x00000000}, |
| 180 | {0xa920, 0x08004b02}, |
| 181 | {0xa924, 0x00000300}, |
| 182 | {0xa928, 0x01000820}, |
| 183 | {0xa92c, 0x00000000}, |
| 184 | {0xa930, 0x00030000}, |
| 185 | {0xa934, 0x15150406}, |
| 186 | {0xa938, 0x00020300}, |
| 187 | {0xa93c, 0x00903900}, |
| 188 | {0xa940, 0x00000000}, |
| 189 | {0xa944, 0x00000000}, |
| 190 | {0xa948, 0x20001b00}, |
| 191 | {0xa94c, 0x0a000010}, |
| 192 | {0xa950, 0x00000000}, |
| 193 | {0xa954, 0x00000008}, |
| 194 | {0xa960, 0x00110000}, |
| 195 | {0xaa3c, 0x00003900}, |
| 196 | {0xaa54, 0x00000008}, |
| 197 | {0xaa60, 0x00110000}, |
| 198 | {0} |
| 199 | }; |
| 200 | |
| 201 | static const struct gt_powermeter ivb_pm_gt2_35w[] = { |
| 202 | {0xa800, 0x00000000}, |
| 203 | {0xa804, 0x00030400}, |
| 204 | {0xa808, 0x00000806}, |
| 205 | {0xa80c, 0x0c002f00}, |
| 206 | {0xa810, 0x0c000300}, |
| 207 | {0xa814, 0x00000000}, |
| 208 | {0xa818, 0x00d20d00}, |
| 209 | {0xa81c, 0x000000ff}, |
| 210 | {0xa820, 0x03004b02}, |
| 211 | {0xa824, 0x00000600}, |
| 212 | {0xa828, 0x07000773}, |
| 213 | {0xa82c, 0x00000000}, |
| 214 | {0xa830, 0x00020032}, |
| 215 | {0xa834, 0x1520040d}, |
| 216 | {0xa838, 0x00020105}, |
| 217 | {0xa83c, 0x00083700}, |
| 218 | {0xa840, 0x000016ff}, |
| 219 | {0xa844, 0x00000000}, |
| 220 | {0xa848, 0xff000000}, |
| 221 | {0xa84c, 0x0a000010}, |
| 222 | {0xa850, 0x00000001}, |
| 223 | {0xa854, 0x00000008}, |
| 224 | {0xa858, 0x00000008}, |
| 225 | {0xa85c, 0x00000000}, |
| 226 | {0xa860, 0x00020000}, |
| 227 | {0xa248, 0x0000221e}, |
| 228 | {0xa900, 0x00000000}, |
| 229 | {0xa904, 0x00003800}, |
| 230 | {0xa908, 0x00000000}, |
| 231 | {0xa90c, 0x0c000000}, |
| 232 | {0xa910, 0x12000800}, |
| 233 | {0xa914, 0x00000000}, |
| 234 | {0xa918, 0x00b20000}, |
| 235 | {0xa91c, 0x00000000}, |
| 236 | {0xa920, 0x08004b02}, |
| 237 | {0xa924, 0x00000300}, |
| 238 | {0xa928, 0x01000820}, |
| 239 | {0xa92c, 0x00000000}, |
| 240 | {0xa930, 0x00030000}, |
| 241 | {0xa934, 0x15150406}, |
| 242 | {0xa938, 0x00020300}, |
| 243 | {0xa93c, 0x00903900}, |
| 244 | {0xa940, 0x00000000}, |
| 245 | {0xa944, 0x00000000}, |
| 246 | {0xa948, 0x20001b00}, |
| 247 | {0xa94c, 0x0a000010}, |
| 248 | {0xa950, 0x00000000}, |
| 249 | {0xa954, 0x00000008}, |
| 250 | {0xa960, 0x00110000}, |
| 251 | {0xaa3c, 0x00003900}, |
| 252 | {0xaa54, 0x00000008}, |
| 253 | {0xaa60, 0x00110000}, |
| 254 | {0} |
| 255 | }; |
| 256 | |
| 257 | /* some vga option roms are used for several chipsets but they only have one |
| 258 | * PCI ID in their header. If we encounter such an option rom, we need to do |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 259 | * the mapping ourselves |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 260 | */ |
| 261 | |
| 262 | u32 map_oprom_vendev(u32 vendev) |
| 263 | { |
| 264 | u32 new_vendev = vendev; |
| 265 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 266 | /* none currently. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 267 | |
| 268 | return new_vendev; |
| 269 | } |
| 270 | |
| 271 | static struct resource *gtt_res = NULL; |
| 272 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 273 | u32 gtt_read(u32 reg) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 274 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 275 | return read32(res2mmio(gtt_res, reg, 0)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 276 | } |
| 277 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 278 | void gtt_write(u32 reg, u32 data) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 279 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 280 | write32(res2mmio(gtt_res, reg, 0), data); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 281 | } |
| 282 | |
| 283 | static inline void gtt_write_powermeter(const struct gt_powermeter *pm) |
| 284 | { |
| 285 | for (; pm && pm->reg; pm++) |
| 286 | gtt_write(pm->reg, pm->value); |
| 287 | } |
| 288 | |
| 289 | #define GTT_RETRY 1000 |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 290 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 291 | { |
| 292 | unsigned try = GTT_RETRY; |
| 293 | u32 data; |
| 294 | |
| 295 | while (try--) { |
| 296 | data = gtt_read(reg); |
| 297 | if ((data & mask) == value) |
| 298 | return 1; |
| 299 | udelay(10); |
| 300 | } |
| 301 | |
| 302 | printk(BIOS_ERR, "GT init timeout\n"); |
| 303 | return 0; |
| 304 | } |
| 305 | |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 306 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 307 | { |
| 308 | const global_nvs_t *gnvs_ptr = gnvs; |
| 309 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 310 | } |
| 311 | |
| 312 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 313 | { |
| 314 | global_nvs_t *gnvs_ptr = gnvs; |
| 315 | if (gnvs_ptr) |
| 316 | gnvs_ptr->aslb = aslb; |
| 317 | } |
| 318 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 319 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 320 | { |
| 321 | u32 reg32; |
| 322 | |
| 323 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 324 | |
| 325 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 326 | if (!gtt_res || !gtt_res->base) |
| 327 | return; |
| 328 | |
| 329 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 330 | /* 1: Enable force wake */ |
| 331 | gtt_write(0xa18c, 0x00000001); |
| 332 | gtt_poll(0x130090, (1 << 0), (1 << 0)); |
| 333 | } else { |
| 334 | gtt_write(0xa180, 1 << 5); |
| 335 | gtt_write(0xa188, 0xffff0001); |
| 336 | gtt_poll(0x130040, (1 << 0), (1 << 0)); |
| 337 | } |
| 338 | |
| 339 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 340 | /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ |
| 341 | reg32 = gtt_read(0x42004); |
| 342 | reg32 |= (1 << 14) | (1 << 15); |
| 343 | gtt_write(0x42004, reg32); |
| 344 | } |
| 345 | |
| 346 | if (bridge_silicon_revision() >= IVB_STEP_A0) { |
| 347 | /* Display Reset Acknowledge Settings */ |
| 348 | reg32 = gtt_read(0x45010); |
| 349 | reg32 |= (1 << 1) | (1 << 0); |
| 350 | gtt_write(0x45010, reg32); |
| 351 | } |
| 352 | |
| 353 | /* 2: Get GT SKU from GTT+0x911c[13] */ |
| 354 | reg32 = gtt_read(0x911c); |
| 355 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 356 | if (reg32 & (1 << 13)) { |
| 357 | printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); |
| 358 | gtt_write_powermeter(snb_pm_gt1); |
| 359 | } else { |
| 360 | printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); |
| 361 | gtt_write_powermeter(snb_pm_gt2); |
| 362 | } |
| 363 | } else { |
| 364 | u32 unit = MCHBAR32(0x5938) & 0xf; |
| 365 | |
| 366 | if (reg32 & (1 << 13)) { |
| 367 | /* GT1 SKU */ |
| 368 | printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); |
| 369 | gtt_write_powermeter(ivb_pm_gt1); |
| 370 | } else { |
| 371 | /* GT2 SKU */ |
| 372 | u32 tdp = MCHBAR32(0x5930) & 0x7fff; |
| 373 | tdp /= (1 << unit); |
| 374 | |
| 375 | if (tdp <= 17) { |
| 376 | /* <=17W ULV */ |
| 377 | printk(BIOS_DEBUG, "IVB GT2 17W " |
| 378 | "Power Meter Weights\n"); |
| 379 | gtt_write_powermeter(ivb_pm_gt2_17w); |
| 380 | } else if ((tdp >= 25) && (tdp <= 35)) { |
| 381 | /* 25W-35W */ |
| 382 | printk(BIOS_DEBUG, "IVB GT2 25W-35W " |
| 383 | "Power Meter Weights\n"); |
| 384 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 385 | } else { |
| 386 | /* All others */ |
| 387 | printk(BIOS_DEBUG, "IVB GT2 35W " |
| 388 | "Power Meter Weights\n"); |
| 389 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 390 | } |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | /* 3: Gear ratio map */ |
| 395 | gtt_write(0xa004, 0x00000010); |
| 396 | |
| 397 | /* 4: GFXPAUSE */ |
| 398 | gtt_write(0xa000, 0x00070020); |
| 399 | |
| 400 | /* 5: Dynamic EU trip control */ |
| 401 | gtt_write(0xa080, 0x00000004); |
| 402 | |
| 403 | /* 6: ECO bits */ |
| 404 | reg32 = gtt_read(0xa180); |
| 405 | reg32 |= (1 << 26) | (1 << 31); |
| 406 | /* (bit 20=1 for SNB step D1+ / IVB A0+) */ |
| 407 | if (bridge_silicon_revision() >= SNB_STEP_D1) |
| 408 | reg32 |= (1 << 20); |
| 409 | gtt_write(0xa180, reg32); |
| 410 | |
| 411 | /* 6a: for SnB step D2+ only */ |
| 412 | if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && |
| 413 | (bridge_silicon_revision() >= SNB_STEP_D2)) { |
| 414 | reg32 = gtt_read(0x9400); |
| 415 | reg32 |= (1 << 7); |
| 416 | gtt_write(0x9400, reg32); |
| 417 | |
| 418 | reg32 = gtt_read(0x941c); |
| 419 | reg32 &= 0xf; |
| 420 | reg32 |= (1 << 1); |
| 421 | gtt_write(0x941c, reg32); |
| 422 | gtt_poll(0x941c, (1 << 1), (0 << 1)); |
| 423 | } |
| 424 | |
| 425 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 426 | reg32 = gtt_read(0x907c); |
| 427 | reg32 |= (1 << 16); |
| 428 | gtt_write(0x907c, reg32); |
| 429 | |
| 430 | /* 6b: Clocking reset controls */ |
| 431 | gtt_write(0x9424, 0x00000001); |
| 432 | } else { |
| 433 | /* 6b: Clocking reset controls */ |
| 434 | gtt_write(0x9424, 0x00000000); |
| 435 | } |
| 436 | |
| 437 | /* 7 */ |
| 438 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { |
| 439 | gtt_write(0x138128, 0x00000029); /* Mailbox Data */ |
| 440 | gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ |
| 441 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) |
| 442 | gtt_write(0x138124, 0x8000000a); |
| 443 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
| 444 | } |
| 445 | |
| 446 | /* 8 */ |
| 447 | gtt_write(0xa090, 0x00000000); /* RC Control */ |
| 448 | gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ |
| 449 | gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ |
| 450 | gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ |
| 451 | gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ |
| 452 | gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ |
| 453 | |
| 454 | /* 9 */ |
| 455 | gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ |
| 456 | gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */ |
| 457 | gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */ |
| 458 | |
| 459 | /* 10 */ |
| 460 | gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ |
| 461 | gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ |
| 462 | gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ |
| 463 | gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ |
| 464 | gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ |
| 465 | |
| 466 | /* 11 */ |
| 467 | gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ |
| 468 | gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ |
| 469 | gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ |
| 470 | gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ |
| 471 | gtt_write(0xa068, 0x000186a0); /* RP Up EI */ |
| 472 | gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ |
| 473 | gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ |
| 474 | |
| 475 | /* 11a: Enable Render Standby (RC6) */ |
| 476 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 477 | /* |
| 478 | * IvyBridge should also support DeepRenderStandby. |
| 479 | * |
| 480 | * Unfortunately it does not work reliably on all SKUs so |
| 481 | * disable it here and it can be enabled by the kernel. |
| 482 | */ |
| 483 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
| 484 | } else { |
| 485 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
| 486 | } |
| 487 | |
| 488 | /* 12: Normal Frequency Request */ |
Felix Held | 6b6c94b | 2017-11-25 00:45:23 +0100 | [diff] [blame] | 489 | /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ |
| 490 | /* only the lower 7 bits are used and shifted left by 25 */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 491 | reg32 = MCHBAR32(0x5998); |
| 492 | reg32 >>= 16; |
Felix Held | 6b6c94b | 2017-11-25 00:45:23 +0100 | [diff] [blame] | 493 | reg32 &= 0x7f; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 494 | reg32 <<= 25; |
| 495 | gtt_write(0xa008, reg32); |
| 496 | |
| 497 | /* 13: RP Control */ |
| 498 | gtt_write(0xa024, 0x00000592); |
| 499 | |
| 500 | /* 14: Enable PM Interrupts */ |
| 501 | gtt_write(0x4402c, 0x03000076); |
| 502 | |
| 503 | /* Clear 0x6c024 [8:6] */ |
| 504 | reg32 = gtt_read(0x6c024); |
| 505 | reg32 &= ~0x000001c0; |
| 506 | gtt_write(0x6c024, reg32); |
| 507 | } |
| 508 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 509 | static void gma_pm_init_post_vbios(struct device *dev) |
| 510 | { |
| 511 | struct northbridge_intel_nehalem_config *conf = dev->chip_info; |
| 512 | u32 reg32; |
| 513 | |
| 514 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 515 | |
| 516 | /* 15: Deassert Force Wake */ |
| 517 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 518 | gtt_write(0xa18c, gtt_read(0xa18c) & ~1); |
| 519 | gtt_poll(0x130090, (1 << 0), (0 << 0)); |
| 520 | } else { |
| 521 | gtt_write(0xa188, 0x1fffe); |
| 522 | if (gtt_poll(0x130040, (1 << 0), (0 << 0))) |
| 523 | gtt_write(0xa188, gtt_read(0xa188) | 1); |
| 524 | } |
| 525 | |
| 526 | /* 16: SW RC Control */ |
| 527 | gtt_write(0xa094, 0x00060000); |
| 528 | |
| 529 | /* Setup Digital Port Hotplug */ |
| 530 | reg32 = gtt_read(0xc4030); |
| 531 | if (!reg32) { |
| 532 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 533 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 534 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 535 | gtt_write(0xc4030, reg32); |
| 536 | } |
| 537 | |
| 538 | /* Setup Panel Power On Delays */ |
| 539 | reg32 = gtt_read(0xc7208); |
| 540 | if (!reg32) { |
| 541 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 542 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 543 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 544 | gtt_write(0xc7208, reg32); |
| 545 | } |
| 546 | |
| 547 | /* Setup Panel Power Off Delays */ |
| 548 | reg32 = gtt_read(0xc720c); |
| 549 | if (!reg32) { |
| 550 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 551 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 552 | gtt_write(0xc720c, reg32); |
| 553 | } |
| 554 | |
| 555 | /* Setup Panel Power Cycle Delay */ |
| 556 | if (conf->gpu_panel_power_cycle_delay) { |
| 557 | reg32 = gtt_read(0xc7210); |
| 558 | reg32 &= ~0xff; |
| 559 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 560 | gtt_write(0xc7210, reg32); |
| 561 | } |
| 562 | |
| 563 | /* Enable Backlight if needed */ |
| 564 | if (conf->gpu_cpu_backlight) { |
| 565 | gtt_write(0x48250, (1 << 31)); |
| 566 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 567 | } |
| 568 | if (conf->gpu_pch_backlight) { |
| 569 | gtt_write(0xc8250, (1 << 31)); |
| 570 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 571 | } |
| 572 | } |
| 573 | |
Patrick Rudolph | 64a702f | 2017-06-20 18:28:56 +0200 | [diff] [blame] | 574 | /* Enable SCI to ACPI _GPE._L06 */ |
| 575 | static void gma_enable_swsci(void) |
| 576 | { |
| 577 | u16 reg16; |
| 578 | |
| 579 | /* clear DMISCI status */ |
| 580 | reg16 = inw(DEFAULT_PMBASE + TCO1_STS); |
| 581 | reg16 &= DMISCI_STS; |
| 582 | outw(DEFAULT_PMBASE + TCO1_STS, reg16); |
| 583 | |
| 584 | /* clear acpi tco status */ |
| 585 | outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); |
| 586 | |
| 587 | /* enable acpi tco scis */ |
| 588 | reg16 = inw(DEFAULT_PMBASE + GPE0_EN); |
| 589 | reg16 |= TCOSCI_EN; |
| 590 | outw(DEFAULT_PMBASE + GPE0_EN, reg16); |
| 591 | } |
| 592 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 593 | static void gma_func0_init(struct device *dev) |
| 594 | { |
| 595 | u32 reg32; |
| 596 | |
| 597 | /* IGD needs to be Bus Master */ |
| 598 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 599 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 600 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 601 | |
| 602 | /* Init graphics power management */ |
| 603 | gma_pm_init_pre_vbios(dev); |
| 604 | |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 605 | if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 606 | struct northbridge_intel_nehalem_config *conf = dev->chip_info; |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 607 | int lightup_ok; |
| 608 | printk(BIOS_SPEW, "Initializing VGA without OPROM."); |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 609 | |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 610 | gma_gfxinit(&lightup_ok); |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 611 | /* Linux relies on VBT for panel info. */ |
| 612 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 613 | "$VBT IRONLAKE-MOBILE"); |
| 614 | } else { |
| 615 | /* PCI Init, will run VBIOS */ |
| 616 | pci_dev_init(dev); |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 617 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 618 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 619 | /* Post VBIOS init */ |
| 620 | gma_pm_init_post_vbios(dev); |
Patrick Rudolph | 64a702f | 2017-06-20 18:28:56 +0200 | [diff] [blame] | 621 | |
| 622 | gma_enable_swsci(); |
| 623 | intel_gma_restore_opregion(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 624 | } |
| 625 | |
Elyes HAOUAS | b60920d | 2018-09-20 17:38:38 +0200 | [diff] [blame] | 626 | static void gma_set_subsystem(struct device *dev, unsigned int vendor, |
| 627 | unsigned int device) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 628 | { |
| 629 | if (!vendor || !device) { |
| 630 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 631 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 632 | } else { |
| 633 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 634 | ((device & 0xffff) << 16) | (vendor & |
| 635 | 0xffff)); |
| 636 | } |
| 637 | } |
| 638 | |
| 639 | static void gma_read_resources(struct device *dev) |
| 640 | { |
| 641 | pci_dev_read_resources(dev); |
| 642 | |
| 643 | struct resource *res; |
| 644 | |
| 645 | /* Set the graphics memory to write combining. */ |
| 646 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 647 | if (res == NULL) { |
| 648 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 649 | return; |
| 650 | } |
| 651 | res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; |
Elyes HAOUAS | cf5430f | 2016-09-13 21:27:22 +0200 | [diff] [blame] | 652 | pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001); |
| 653 | pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 654 | res->base = (resource_t) 0xd0000000; |
| 655 | res->size = (resource_t) 0x10000000; |
| 656 | } |
| 657 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 658 | const struct i915_gpu_controller_info * |
| 659 | intel_gma_get_controller_info(void) |
| 660 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 661 | struct device *dev = pcidev_on_root(0x2, 0); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 662 | if (!dev) { |
| 663 | return NULL; |
| 664 | } |
| 665 | struct northbridge_intel_nehalem_config *chip = dev->chip_info; |
| 666 | return &chip->gfx; |
| 667 | } |
| 668 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 669 | static void gma_ssdt(struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 670 | { |
| 671 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 672 | if (!gfx) { |
| 673 | return; |
| 674 | } |
| 675 | |
| 676 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 677 | } |
| 678 | |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 679 | static unsigned long |
| 680 | gma_write_acpi_tables(struct device *const dev, |
| 681 | unsigned long current, |
| 682 | struct acpi_rsdp *const rsdp) |
| 683 | { |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 684 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 685 | global_nvs_t *gnvs; |
| 686 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 687 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 688 | return current; |
| 689 | |
| 690 | current += sizeof(igd_opregion_t); |
| 691 | |
| 692 | /* GNVS has been already set up */ |
| 693 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 694 | if (gnvs) { |
| 695 | /* IGD OpRegion Base Address */ |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 696 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 697 | } else { |
| 698 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 699 | } |
| 700 | |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 701 | current = acpi_align_current(current); |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 702 | return current; |
| 703 | } |
| 704 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 705 | static struct pci_operations gma_pci_ops = { |
| 706 | .set_subsystem = gma_set_subsystem, |
| 707 | }; |
| 708 | |
| 709 | static struct device_operations gma_func0_ops = { |
| 710 | .read_resources = gma_read_resources, |
| 711 | .set_resources = pci_dev_set_resources, |
| 712 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 713 | .acpi_fill_ssdt_generator = gma_ssdt, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 714 | .init = gma_func0_init, |
| 715 | .scan_bus = 0, |
| 716 | .enable = 0, |
| 717 | .ops_pci = &gma_pci_ops, |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 718 | .write_acpi_tables = gma_write_acpi_tables, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 719 | }; |
| 720 | |
Elyes HAOUAS | cf5430f | 2016-09-13 21:27:22 +0200 | [diff] [blame] | 721 | static const unsigned short pci_device_ids[] = { |
| 722 | 0x0046, 0x0102, 0x0106, 0x010a, 0x0112, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 723 | 0x0116, 0x0122, 0x0126, 0x0156, |
| 724 | 0x0166, |
| 725 | 0 |
| 726 | }; |
| 727 | |
| 728 | static const struct pci_driver gma __pci_driver = { |
| 729 | .ops = &gma_func0_ops, |
| 730 | .vendor = PCI_VENDOR_ID_INTEL, |
| 731 | .devices = pci_device_ids, |
| 732 | }; |