blob: c0b0b8d3d8521b14ffcc1d2ac5c0f4e30a5e7001 [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
17/* Global Variables */
18
Lee Leahy32471722015-04-20 15:20:28 -070019Name(\PICM, 0) /* IOAPIC/8259 */
Lee Leahy77ff0b12015-05-05 15:07:29 -070020
Lee Leahy32471722015-04-20 15:20:28 -070021/*
22 * Global ACPI memory region. This region is used for passing information
Lee Leahy77ff0b12015-05-05 15:07:29 -070023 * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
24 * Since we don't know where this will end up in memory at ACPI compile time,
25 * we have to fix it up in coreboot's ACPI creation phase.
26 */
27
Hannah Williams51668272016-01-28 14:25:32 -080028External (NVSA)
Lee Leahy77ff0b12015-05-05 15:07:29 -070029
Hannah Williams51668272016-01-28 14:25:32 -080030OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Lee Leahy77ff0b12015-05-05 15:07:29 -070031Field (GNVS, ByteAcc, NoLock, Preserve)
32{
33 /* Miscellaneous */
34 Offset (0x00),
Lee Leahy32471722015-04-20 15:20:28 -070035 OSYS, 16, /* 0x00 - Operating System */
36 SMIF, 8, /* 0x02 - SMI function */
37 PRM0, 8, /* 0x03 - SMI function parameter */
38 PRM1, 8, /* 0x04 - SMI function parameter */
39 SCIF, 8, /* 0x05 - SCI function */
40 PRM2, 8, /* 0x06 - SCI function parameter */
41 PRM3, 8, /* 0x07 - SCI function parameter */
42 LCKF, 8, /* 0x08 - Global Lock function for EC */
43 PRM4, 8, /* 0x09 - Lock function parameter */
44 PRM5, 8, /* 0x0a - Lock function parameter */
45 P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
46 LIDS, 8, /* 0x0f - LID state (open = 1) */
47 PWRS, 8, /* 0x10 - Power State (AC = 1) */
48 PCNT, 8, /* 0x11 - Processor count */
49 TPMP, 8, /* 0x12 - TPM Present and Enabled */
50 TLVL, 8, /* 0x13 - Throttle Level */
51 PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
52 PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
Duncan Lauriee73da802015-09-08 16:16:34 -070053 GPEI, 32, /* 0x19 - GPE Wake Source */
54 BDID, 8, /* 0x1d - Board ID */
Hannah Williamsba6dfe42016-01-26 15:40:24 -080055 CID1, 16, /* 0x1e - Wifi Domain Type */
Lee Leahy77ff0b12015-05-05 15:07:29 -070056
57 /* Device Config */
58 Offset (0x20),
Lee Leahy32471722015-04-20 15:20:28 -070059 S5U0, 8, /* 0x20 - Enable USB0 in S5 */
60 S5U1, 8, /* 0x21 - Enable USB1 in S5 */
61 S3U0, 8, /* 0x22 - Enable USB0 in S3 */
62 S3U1, 8, /* 0x23 - Enable USB1 in S3 */
63 TACT, 8, /* 0x24 - Thermal Active trip point */
64 TPSV, 8, /* 0x25 - Thermal Passive trip point */
65 TCRT, 8, /* 0x26 - Thermal Critical trip point */
66 DPTE, 8, /* 0x27 - Enable DPTF */
Lee Leahy77ff0b12015-05-05 15:07:29 -070067
68 /* Base addresses */
69 Offset (0x30),
Lee Leahy32471722015-04-20 15:20:28 -070070 CMEM, 32, /* 0x30 - CBMEM TOC */
71 TOLM, 32, /* 0x34 - Top of Low Memory */
72 CBMC, 32, /* 0x38 - coreboot mem console pointer */
Lee Leahy77ff0b12015-05-05 15:07:29 -070073
Matt DeVillier132bbe62017-07-01 13:02:47 -050074 /* IGD OpRegion */
75 Offset (0xb4),
76 ASLB, 32, // 0xb4 - IGD OpRegion Base Address
77 IBTT, 8, // 0xb8 - IGD boot panel device
78 IPAT, 8, // 0xb9 - IGD panel type cmos option
79 ITVF, 8, // 0xba - IGD TV format cmos option
80 ITVM, 8, // 0xbb - IGD TV minor format option
81 IPSC, 8, // 0xbc - IGD panel scaling
82 IBLC, 8, // 0xbd - IGD BLC config
83 IBIA, 8, // 0xbe - IGD BIA config
84 ISSC, 8, // 0xbf - IGD SSC config
85 I409, 8, // 0xc0 - IGD 0409 modified settings
86 I509, 8, // 0xc1 - IGD 0509 modified settings
87 I609, 8, // 0xc2 - IGD 0609 modified settings
88 I709, 8, // 0xc3 - IGD 0709 modified settings
89 IDMM, 8, // 0xc4 - IGD Power conservation feature
90 IDMS, 8, // 0xc5 - IGD DVMT memory size
91 IF1E, 8, // 0xc6 - IGD function 1 enable
92 HVCO, 8, // 0xc7 - IGD HPLL VCO
93 NXD1, 32, // 0xc8 - IGD _DGS next DID1
94 NXD2, 32, // 0xcc - IGD _DGS next DID2
95 NXD3, 32, // 0xd0 - IGD _DGS next DID3
96 NXD4, 32, // 0xd4 - IGD _DGS next DID4
97 NXD5, 32, // 0xd8 - IGD _DGS next DID5
98 NXD6, 32, // 0xdc - IGD _DGS next DID6
99 NXD7, 32, // 0xe0 - IGD _DGS next DID7
100 NXD8, 32, // 0xe4 - IGD _DGS next DID8
101
102 ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)
103 PAVP, 8, // 0xe9 - IGD PAVP data
104 Offset (0xeb),
105 OSCC, 8, // 0xeb - PCIe OSC control
106 NPCE, 8, // 0xec - native pcie support
107 PLFL, 8, // 0xed - platform flavor
108 BREV, 8, // 0xee - board revision
109 DPBM, 8, // 0xef - digital port b mode
110 DPCM, 8, // 0xf0 - digital port c mode
111 DPDM, 8, // 0xf1 - digital port d mode
112 ALFP, 8, // 0xf2 - active lfp
113 IMON, 8, // 0xf3 - current graphics turbo imon value
114 MMIO, 8, // 0xf4 - 64bit mmio support
115
Lee Leahy77ff0b12015-05-05 15:07:29 -0700116 /* ChromeOS specific */
117 Offset (0x100),
118 #include <vendorcode/google/chromeos/acpi/gnvs.asl>
119
120 Offset (0x1000),
Lee Leahy32471722015-04-20 15:20:28 -0700121 #include <soc/intel/braswell/acpi/device_nvs.asl>
Lee Leahy77ff0b12015-05-05 15:07:29 -0700122}
123
124/* Set flag to enable USB charging in S3 */
125Method (S3UE)
126{
127 Store (One, \S3U0)
128 Store (One, \S3U1)
129}
130
131/* Set flag to disable USB charging in S3 */
132Method (S3UD)
133{
134 Store (Zero, \S3U0)
135 Store (Zero, \S3U1)
136}
137
138/* Set flag to enable USB charging in S5 */
139Method (S5UE)
140{
141 Store (One, \S5U0)
142 Store (One, \S5U1)
143}
144
145/* Set flag to disable USB charging in S5 */
146Method (S5UD)
147{
148 Store (Zero, \S5U0)
149 Store (Zero, \S5U1)
150}