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Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2011 Google Inc
6 * Copyright (C) 2013 Vladimir Serbinenko
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010016 */
17
18#include <stdint.h>
19#include <stdlib.h>
20#include <console/console.h>
21#include <arch/io.h>
22#include <device/pci_def.h>
23#include <elog.h>
24#include <cpu/x86/msr.h>
25#include <cpu/intel/speedstep.h>
26#include <cpu/intel/turbo.h>
27#include <arch/cpu.h>
Arthur Heymansd2d2aef2018-01-16 14:19:37 +010028#include <southbridge/intel/common/rcba.h>
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010029
30#include "nehalem.h"
31
32static void nehalem_setup_bars(void)
33{
34 /* Setting up Southbridge. In the northbridge code. */
35 printk(BIOS_DEBUG, "Setting up static southbridge registers...");
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080036 pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010037
38 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
39 /* Enable ACPI BAR */
40 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
41
42 printk(BIOS_DEBUG, " done.\n");
43
44 printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
45 /* No reset */
46 RCBA32(GCS) = RCBA32(GCS) | (1 << 5);
47 /* halt timer */
48 outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
49 /* halt timer */
50 outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2,
51 DEFAULT_PMBASE | 0x60 | 0x06);
52 printk(BIOS_DEBUG, " done.\n");
53
54 printk(BIOS_DEBUG, "Setting up static northbridge registers...");
55 /* Set up all hardcoded northbridge BARs */
56 pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
57 pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
58 (0LL + DEFAULT_EPBAR) >> 32);
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080059 pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010060 pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080061 (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010062
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080063 pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010064 pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080065 (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010066
67 /* Set C0000-FFFFF to access RAM on both reads and writes */
68 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
69 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33);
70 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33);
71 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33);
72 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33);
73 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
74 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
75
Martin Roth33232602017-06-24 14:48:50 -060076#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010077 /* Increment Boot Counter for non-S3 resume */
78 if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
79 ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
80 boot_count_increment();
81#endif
82
83 printk(BIOS_DEBUG, " done.\n");
84
Martin Roth33232602017-06-24 14:48:50 -060085#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010086 /* Increment Boot Counter except when resuming from S3 */
87 if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
88 ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
89 return;
90 boot_count_increment();
91#endif
92}
93
94static void early_cpu_init (void)
95{
96 msr_t m;
97
98 /* bit 0 = disable multicore,
99 bit 1 = disable quadcore,
100 bit 8 = disable hyperthreading. */
101 pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80,
102 (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000);
103
104 u8 reg8;
105 struct cpuid_result result;
106 result = cpuid_ext(0x6, 0x8b);
107 if (!(result.eax & 0x2)) {
108 m = rdmsr(MSR_FSB_CLOCK_VCC);
109 reg8 = ((m.lo & 0xff00) >> 8) + 1;
110 m = rdmsr (IA32_PERF_CTL);
111 m.lo = (m.lo & ~0xff) | reg8;
112 wrmsr(IA32_PERF_CTL, m);
113
114 m = rdmsr(MSR_IA32_MISC_ENABLES);
115 m.hi &= ~0x00000040;
116 m.lo |= 0x10000;
117
118 wrmsr(MSR_IA32_MISC_ENABLES, m);
119 }
120
121 m = rdmsr(MSR_FSB_CLOCK_VCC);
122 reg8 = ((m.lo & 0xff00) >> 8) + 1;
123
124 m = rdmsr (IA32_PERF_CTL);
125 m.lo = (m.lo & ~0xff) | reg8;
126 wrmsr(IA32_PERF_CTL, m);
127
128 m = rdmsr(MSR_IA32_MISC_ENABLES);
129 m.lo |= 0x10000;
130 wrmsr(MSR_IA32_MISC_ENABLES, m);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +0100131}
132
133void nehalem_early_initialization(int chipset_type)
134{
135 u32 capid0_a;
136 u8 reg8;
137
138 /* Device ID Override Enable should be done very early */
139 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
140 if (capid0_a & (1 << 10)) {
141 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
142 reg8 &= ~7; /* Clear 2:0 */
143
144 if (chipset_type == NEHALEM_MOBILE)
145 reg8 |= 1; /* Set bit 0 */
146
147 pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
148 }
149
150 /* Setup all BARs required for early PCIe and raminit */
151 nehalem_setup_bars();
152
153 /* Device Enable */
154 pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, 9 | 2);
155
156 early_cpu_init();
157
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800158 pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +0100159 pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
160 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
Vladimir Serbinenkobca98552014-01-09 11:13:18 +0100161
162 /* Magic for S3 resume. Must be done early. */
163 if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) {
164 MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
165 MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
166 }
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +0100167}