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Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010014 */
15
Iru Caid7ee9dd2016-02-24 15:03:58 +080016#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
17#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H
18
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +020019#include <drivers/intel/gma/i915.h>
20
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010021/*
22 * Digital Port Hotplug Enable:
23 * 0x04 = Enabled, 2ms short pulse
24 * 0x05 = Enabled, 4.5ms short pulse
25 * 0x06 = Enabled, 6ms short pulse
26 * 0x07 = Enabled, 100ms short pulse
27 */
28struct northbridge_intel_nehalem_config {
29 u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
30 u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
31 u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
32
33 u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
34 u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
35 u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
36 u16 gpu_panel_power_down_delay; /* T3 time sequence */
37 u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
38 u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
39
40 u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
41 u32 gpu_pch_backlight; /* PCH Backlight PWM value */
Vladimir Serbinenko13157302014-02-19 22:18:08 +010042
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +020043 struct i915_gpu_controller_info gfx;
Patrick Rudolph266a1f72016-06-09 18:13:34 +020044
45 /*
46 * Maximum PCI mmio size in MiB.
47 */
48 u16 pci_mmio_size;
Vladimir Serbinenkoc6f6be02013-11-12 22:32:08 +010049};
Iru Caid7ee9dd2016-02-24 15:03:58 +080050
51#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */