blob: 04f73566db0e1d9941337a6417561cdb5bcca699 [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Aaron Durbin76c37002012-10-30 09:03:43 -050015 */
16
17#include <arch/io.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050018#include <stdlib.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050019#include "haswell.h"
20
Aaron Durbin89f79a02012-10-31 23:05:25 -050021#define PCI_DEV_HSW PCI_DEV(0, 0, 0)
Aaron Durbin76c37002012-10-30 09:03:43 -050022
23void intel_northbridge_haswell_finalize_smm(void)
24{
Aaron Durbin89f79a02012-10-31 23:05:25 -050025 pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0); /* GGC */
26 pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0); /* DPR */
27 pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10); /* ME */
28 pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0); /* REMAPBASE */
29 pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0); /* REMAPLIMIT */
30 pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0); /* TOM */
31 pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0); /* TOUUD */
32 pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0); /* BDSM */
33 pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0); /* BGSM */
34 pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */
35 pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */
Aaron Durbin76c37002012-10-30 09:03:43 -050036
37 MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
Ryan Salsamendib9bc2572017-07-04 13:35:06 -070038 MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */
Aaron Durbin76c37002012-10-30 09:03:43 -050039 MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
40 MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
Ryan Salsamendib9bc2572017-07-04 13:35:06 -070041 MCHBAR32_OR(0x6800, 1UL << 31);
42 MCHBAR32_OR(0x7000, 1UL << 31);
Aaron Durbin76c37002012-10-30 09:03:43 -050043 MCHBAR32_OR(0x77fc, 1 << 0);
44
45 /* Memory Controller Lockdown */
46 MCHBAR8(0x50fc) = 0x8f;
47
48 /* Read+write the following */
49 MCHBAR32(0x6030) = MCHBAR32(0x6030);
50 MCHBAR32(0x6034) = MCHBAR32(0x6034);
51 MCHBAR32(0x6008) = MCHBAR32(0x6008);
52}