Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/byteorder.h> |
| 26 | #include <arch/io.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 27 | #include <device/pci.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <device/pnp_def.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | #include <pc80/mc146818rtc.h> |
| 32 | #include <cbmem.h> |
| 33 | #include <console/console.h> |
| 34 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 35 | #include "northbridge/intel/sandybridge/raminit.h" |
| 36 | #include "southbridge/intel/bd82x6x/pch.h" |
| 37 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 38 | #include "ec/google/chromeec/ec.h" |
| 39 | #include <arch/cpu.h> |
| 40 | #include <cpu/x86/bist.h> |
| 41 | #include <cpu/x86/msr.h> |
| 42 | #include "gpio.h" |
| 43 | #if CONFIG_CHROMEOS |
| 44 | #include <vendorcode/google/chromeos/chromeos.h> |
| 45 | #endif |
| 46 | #include <cbfs.h> |
| 47 | |
| 48 | #include <southbridge/intel/bd82x6x/chip.h> |
| 49 | |
| 50 | static void pch_enable_lpc(void) |
| 51 | { |
| 52 | const struct device *lpc; |
| 53 | const struct southbridge_intel_bd82x6x_config *config = NULL; |
| 54 | |
| 55 | lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); |
| 56 | if (!lpc) |
| 57 | return; |
| 58 | if (lpc->chip_info) |
| 59 | config = lpc->chip_info; |
| 60 | if (!config) |
| 61 | return; |
| 62 | |
| 63 | /* Set COM1/COM2 decode range */ |
| 64 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 65 | |
| 66 | /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ |
| 67 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ |
| 68 | GAMEL_LPC_EN | COMA_LPC_EN); |
| 69 | |
| 70 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 71 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 72 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 73 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
| 74 | } |
| 75 | |
| 76 | static void rcba_config(void) |
| 77 | { |
| 78 | u32 reg32; |
| 79 | |
| 80 | /* |
| 81 | * GFX INTA -> PIRQA (MSI) |
| 82 | * D28IP_P3IP WLAN INTA -> PIRQB |
| 83 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 84 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 85 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 86 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 87 | * D31IP_TTIP THRT INTC -> PIRQA |
| 88 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 89 | * |
| 90 | * TRACKPAD -> PIRQE (Edge Triggered) |
| 91 | * TOUCHSCREEN -> PIRQG (Edge Triggered) |
| 92 | */ |
| 93 | |
| 94 | /* Device interrupt pin register (board specific) */ |
| 95 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 96 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 97 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 98 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 99 | RCBA32(D28IP) = (INTA << D28IP_P3IP); |
| 100 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 101 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 102 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 103 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 104 | |
| 105 | /* Device interrupt route registers */ |
| 106 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 107 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 108 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 109 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 110 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 111 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 112 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 113 | |
| 114 | /* Enable IOAPIC (generic) */ |
| 115 | RCBA16(OIC) = 0x0100; |
| 116 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 117 | (void) RCBA16(OIC); |
| 118 | |
| 119 | /* Disable unused devices (board specific) */ |
| 120 | reg32 = RCBA32(FD); |
| 121 | reg32 |= PCH_DISABLE_ALWAYS; |
| 122 | RCBA32(FD) = reg32; |
| 123 | } |
| 124 | |
| 125 | static void copy_spd(struct pei_data *peid) |
| 126 | { |
| 127 | const int gpio_vector[] = {41, 42, 43, 10, -1}; |
| 128 | struct cbfs_file *spd_file; |
| 129 | int spd_index = get_gpios(gpio_vector); |
| 130 | |
| 131 | printk(BIOS_DEBUG, "spd index %d\n", spd_index); |
| 132 | spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); |
| 133 | if (!spd_file) |
| 134 | die("SPD data not found."); |
| 135 | |
| 136 | if (ntohl(spd_file->len) < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { |
| 137 | printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); |
| 138 | spd_index = 0; |
| 139 | } |
| 140 | |
| 141 | if (spd_file->len < sizeof(peid->spd_data[0])) |
| 142 | die("Missing SPD data."); |
| 143 | |
| 144 | memcpy(peid->spd_data[0], |
| 145 | ((char*)CBFS_SUBHEADER(spd_file)) + |
| 146 | spd_index * sizeof(peid->spd_data[0]), |
| 147 | sizeof(peid->spd_data[0])); |
| 148 | } |
| 149 | |
| 150 | void main(unsigned long bist) |
| 151 | { |
| 152 | int boot_mode = 0; |
| 153 | int cbmem_was_initted; |
| 154 | u32 pm1_cnt; |
| 155 | u16 pm1_sts; |
| 156 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 157 | struct pei_data pei_data = { |
| 158 | pei_version: PEI_VERSION, |
| 159 | mchbar: DEFAULT_MCHBAR, |
| 160 | dmibar: DEFAULT_DMIBAR, |
| 161 | epbar: DEFAULT_EPBAR, |
| 162 | pciexbar: CONFIG_MMCONF_BASE_ADDRESS, |
| 163 | smbusbar: SMBUS_IO_BASE, |
| 164 | wdbbar: 0x4000000, |
| 165 | wdbsize: 0x1000, |
| 166 | hpet_address: CONFIG_HPET_ADDRESS, |
| 167 | rcba: DEFAULT_RCBABASE, |
| 168 | pmbase: DEFAULT_PMBASE, |
| 169 | gpiobase: DEFAULT_GPIOBASE, |
| 170 | thermalbase: 0xfed08000, |
| 171 | system_type: 0, // 0 Mobile, 1 Desktop/Server |
| 172 | tseg_size: CONFIG_SMM_TSEG_SIZE, |
| 173 | ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, |
| 174 | ec_present: 1, |
| 175 | ddr3lv_support: 1, |
| 176 | // 0 = leave channel enabled |
| 177 | // 1 = disable dimm 0 on channel |
| 178 | // 2 = disable dimm 1 on channel |
| 179 | // 3 = disable dimm 0+1 on channel |
| 180 | dimm_channel0_disabled: 2, |
| 181 | dimm_channel1_disabled: 2, |
| 182 | max_ddr3_freq: 1600, |
| 183 | usb_port_config: { |
| 184 | /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ |
| 185 | { 0, 3, 0x0000 }, /* P0: Empty */ |
| 186 | { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ |
| 187 | { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ |
| 188 | { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ |
| 189 | { 0, 3, 0x0000 }, /* P4: Empty */ |
| 190 | { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ |
| 191 | { 0, 3, 0x0000 }, /* P6: Empty */ |
| 192 | { 0, 3, 0x0000 }, /* P7: Empty */ |
| 193 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 194 | { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ |
| 195 | { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ |
| 196 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 197 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 198 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 199 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 200 | }, |
| 201 | }; |
| 202 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 203 | timestamp_init(get_initial_timestamp()); |
| 204 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 205 | |
| 206 | if (bist == 0) |
| 207 | enable_lapic(); |
| 208 | |
| 209 | pch_enable_lpc(); |
| 210 | |
| 211 | /* Enable GPIOs */ |
| 212 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 213 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 214 | setup_pch_gpios(&link_gpio_map); |
| 215 | |
| 216 | /* Initialize console device(s) */ |
| 217 | console_init(); |
| 218 | |
| 219 | /* Halt if there was a built in self test failure */ |
| 220 | report_bist_failure(bist); |
| 221 | |
| 222 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 223 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 224 | boot_mode = 1; |
| 225 | |
| 226 | /* System is not happy after keyboard reset... */ |
| 227 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 228 | outb(0x6, 0xcf9); |
| 229 | hlt(); |
| 230 | } |
| 231 | |
| 232 | /* Perform some early chipset initialization required |
| 233 | * before RAM initialization can work |
| 234 | */ |
| 235 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 236 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 237 | |
| 238 | /* Check PM1_STS[15] to see if we are waking from Sx */ |
| 239 | pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); |
| 240 | |
| 241 | /* Read PM1_CNT[12:10] to determine which Sx state */ |
| 242 | pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); |
| 243 | |
| 244 | if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { |
| 245 | #if CONFIG_HAVE_ACPI_RESUME |
| 246 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 247 | boot_mode = 2; |
| 248 | /* Clear SLP_TYPE. This will break stage2 but |
| 249 | * we care for that when we get there. |
| 250 | */ |
| 251 | outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); |
| 252 | #else |
| 253 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
| 254 | #endif |
| 255 | } else { |
| 256 | /* This is the fastest way to let users know |
| 257 | * the Intel CPU is now alive. |
| 258 | */ |
| 259 | google_chromeec_kbbacklight(100); |
| 260 | } |
| 261 | |
| 262 | post_code(0x38); |
| 263 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 264 | enable_smbus(); |
| 265 | |
| 266 | /* Prepare USB controller early in S3 resume */ |
| 267 | if (boot_mode == 2) |
| 268 | enable_usb_bar(); |
| 269 | |
| 270 | post_code(0x39); |
| 271 | |
| 272 | copy_spd(&pei_data); |
| 273 | |
| 274 | post_code(0x3a); |
| 275 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 276 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 277 | sdram_initialize(&pei_data); |
| 278 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 279 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 280 | post_code(0x3c); |
| 281 | |
| 282 | rcba_config(); |
| 283 | post_code(0x3d); |
| 284 | |
| 285 | quick_ram_check(); |
| 286 | post_code(0x3e); |
| 287 | |
| 288 | MCHBAR16(SSKPD) = 0xCAFE; |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 289 | cbmem_was_initted = !cbmem_initialize(); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 290 | |
| 291 | #if CONFIG_HAVE_ACPI_RESUME |
| 292 | /* If there is no high memory area, we didn't boot before, so |
| 293 | * this is not a resume. In that case we just create the cbmem toc. |
| 294 | */ |
| 295 | |
| 296 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 297 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 298 | |
| 299 | if ((boot_mode == 2) && cbmem_was_initted) { |
| 300 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 301 | if (resume_backup_memory) { |
| 302 | *(u32 *)CBMEM_BOOT_MODE = boot_mode; |
| 303 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 304 | } |
| 305 | /* Magic for S3 resume */ |
| 306 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 307 | } else if (boot_mode == 2) { |
| 308 | /* Failed S3 resume, reset to come up cleanly */ |
| 309 | outb(0x6, 0xcf9); |
| 310 | hlt(); |
| 311 | } else { |
| 312 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 313 | } |
| 314 | #endif |
| 315 | post_code(0x3f); |
| 316 | #if CONFIG_CHROMEOS |
| 317 | init_chromeos(boot_mode); |
| 318 | #endif |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 319 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 320 | } |