Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 LiPPERT Embedded Computers GmbH |
| 5 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 6 | * |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Stefan Reinauer | 38f147e | 2010-02-08 12:20:50 +0000 | [diff] [blame] | 22 | /* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */ |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame] | 23 | |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 24 | #include <stdlib.h> |
| 25 | #include <stdint.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <arch/hlt.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame^] | 30 | #include <console/console.h> |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 31 | #include "lib/ramtest.c" |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 32 | #include "cpu/x86/bist.h" |
| 33 | #include "cpu/x86/msr.h" |
| 34 | #include <cpu/amd/lxdef.h> |
| 35 | #include <cpu/amd/geode_post_code.h> |
| 36 | #include "southbridge/amd/cs5536/cs5536.h" |
| 37 | |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 38 | #include "southbridge/amd/cs5536/cs5536_early_smbus.c" |
| 39 | #include "southbridge/amd/cs5536/cs5536_early_setup.c" |
| 40 | #include "superio/ite/it8712f/it8712f_early_serial.c" |
| 41 | |
| 42 | #define ManualConf 1 /* No automatic strapped PLL config */ |
| 43 | #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ |
| 44 | #define PLLMSRlo 0x00DE6001 |
| 45 | #define DIMM0 0xA0 |
| 46 | #define DIMM1 0xA2 |
| 47 | |
| 48 | static inline int spd_read_byte(unsigned int device, unsigned int address) |
| 49 | { |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame] | 50 | if (device != DIMM0) |
| 51 | return 0xFF; /* No DIMM1, don't even try. */ |
| 52 | |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 53 | return smbus_read_byte(device, address); |
| 54 | } |
| 55 | |
| 56 | #include "northbridge/amd/lx/raminit.h" |
| 57 | #include "northbridge/amd/lx/pll_reset.c" |
| 58 | #include "northbridge/amd/lx/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 59 | #include "lib/generic_sdram.c" |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 60 | #include "cpu/amd/model_lx/cpureginit.c" |
| 61 | #include "cpu/amd/model_lx/syspreinit.c" |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 62 | #include "cpu/amd/model_lx/msrinit.c" |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 63 | |
| 64 | static const u16 sio_init_table[] = { // hi=data, lo=index |
| 65 | 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) |
| 66 | 0x1E2C, // disable ATXPowerGood - will cause a reboot! |
| 67 | 0x0423, // don't delay POWerOK1/2 |
| 68 | 0x9072, // watchdog triggers POWOK, counts seconds |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 69 | #if !CONFIG_USE_WATCHDOG_ON_BOOT |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 70 | 0x0073, 0x0074, // disable watchdog by setting timeout to 0 |
| 71 | #endif |
| 72 | 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins |
| 73 | 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) |
| 74 | 0x1E2C, // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled |
| 75 | 0x46B8, 0x0CB9, // enable pullups |
| 76 | 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 |
| 77 | 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) |
| 78 | 0x26C8, // config GP15,12,11 as output; GP14 as input |
| 79 | 0x2DF5, // map Hw Monitor Thermal Output to GP55 |
| 80 | 0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use) |
| 81 | }; |
| 82 | |
| 83 | /* Early mainboard specific GPIO setup. */ |
| 84 | static void mb_gpio_init(void) |
| 85 | { |
| 86 | int i; |
| 87 | |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame] | 88 | /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 89 | it8712f_enter_conf(); |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame] | 90 | for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 91 | u16 val = sio_init_table[i]; |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame] | 92 | outb((u8)val, SIO_INDEX); |
| 93 | outb(val >> 8, SIO_DATA); |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 94 | } |
| 95 | it8712f_exit_conf(); |
| 96 | } |
| 97 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 98 | void main(unsigned long bist) |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 99 | { |
Stefan Reinauer | 0c781b2 | 2010-04-01 09:50:32 +0000 | [diff] [blame] | 100 | post_code(0x01); |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 101 | |
| 102 | static const struct mem_controller memctrl[] = { |
| 103 | {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} |
| 104 | }; |
| 105 | |
| 106 | SystemPreInit(); |
| 107 | msr_init(); |
| 108 | |
| 109 | cs5536_early_setup(); |
| 110 | |
Uwe Hermann | 86c9b88 | 2008-11-19 13:42:14 +0000 | [diff] [blame] | 111 | /* |
| 112 | * Note: must do this AFTER the early_setup! It is counting on some |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 113 | * early MSR setup for CS5536. |
| 114 | */ |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 115 | it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 116 | mb_gpio_init(); |
| 117 | uart_init(); |
| 118 | console_init(); |
| 119 | |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 120 | /* Halt if there was a built in self test failure */ |
| 121 | report_bist_failure(bist); |
| 122 | |
Jens Rottmann | f31ca16 | 2008-11-19 12:19:09 +0000 | [diff] [blame] | 123 | pll_reset(ManualConf); |
| 124 | |
| 125 | cpuRegInit(); |
| 126 | |
| 127 | sdram_initialize(1, memctrl); |
| 128 | |
| 129 | /* Check memory. */ |
| 130 | /* ram_check(0x00000000, 640 * 1024); */ |
| 131 | |
| 132 | /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ |
| 133 | return; |
| 134 | } |
Stefan Reinauer | 798ef28 | 2010-03-29 22:08:01 +0000 | [diff] [blame] | 135 | |