Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | |
| 4 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <console/console.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <arch/acpi.h> |
| 7 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include "haswell.h" |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 10 | #include <southbridge/intel/lynxpoint/pch.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 11 | |
| 12 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 13 | { |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 14 | struct device *dev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | u32 pciexbar = 0; |
| 16 | u32 pciexbar_reg; |
| 17 | int max_buses; |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 18 | u32 mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 20 | dev = pcidev_on_root(0, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 21 | if (!dev) |
| 22 | return current; |
| 23 | |
Elyes HAOUAS | 69d658f | 2016-09-17 20:32:07 +0200 | [diff] [blame] | 24 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 26 | /* MMCFG not supported or not enabled. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 27 | if (!(pciexbar_reg & (1 << 0))) |
| 28 | return current; |
| 29 | |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 30 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | switch ((pciexbar_reg >> 1) & 3) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 32 | case 0: /* 256MB */ |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 33 | pciexbar = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | max_buses = 256; |
| 35 | break; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 36 | case 1: /* 128M */ |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 37 | mask |= (1 << 27); |
| 38 | pciexbar = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 39 | max_buses = 128; |
| 40 | break; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 41 | case 2: /* 64M */ |
Ryan Salsamendi | b9bc257 | 2017-07-04 13:35:06 -0700 | [diff] [blame] | 42 | mask |= (1 << 27) | (1 << 26); |
| 43 | pciexbar = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 44 | max_buses = 64; |
| 45 | break; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 46 | default: /* RSVD */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | return current; |
| 48 | } |
| 49 | |
| 50 | if (!pciexbar) |
| 51 | return current; |
| 52 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 53 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, |
| 54 | max_buses - 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | |
| 56 | return current; |
| 57 | } |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 58 | |
| 59 | static unsigned long acpi_fill_dmar(unsigned long current) |
| 60 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 61 | struct device *const igfx_dev = pcidev_on_root(2, 0); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 62 | const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; |
| 63 | const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; |
| 64 | const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; |
| 65 | const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; |
| 66 | |
| 67 | /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 68 | if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { |
| 69 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 70 | const unsigned long tmp = current; |
| 71 | |
| 72 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
Matt DeVillier | 7866d49 | 2018-03-29 14:59:57 +0200 | [diff] [blame] | 73 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 74 | |
| 75 | acpi_dmar_drhd_fixup(tmp, current); |
| 76 | } |
| 77 | |
| 78 | /* VTVC0BAR has to be set, enabled, and in 32-bit space */ |
| 79 | if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 80 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 81 | const unsigned long tmp = current; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 82 | current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
| 83 | current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, |
| 84 | PCH_IOAPIC_PCI_SLOT, 0); |
| 85 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 86 | size_t i; |
| 87 | for (i = 0; i < 8; ++i) |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 88 | current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, |
| 89 | PCH_HPET_PCI_SLOT, i); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 90 | acpi_dmar_drhd_fixup(tmp, current); |
| 91 | } |
| 92 | |
| 93 | return current; |
| 94 | } |
| 95 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 96 | unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 97 | struct acpi_rsdp *const rsdp) |
| 98 | { |
| 99 | /* Create DMAR table only if we have VT-d capability. */ |
| 100 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
| 101 | if (capid0_a & VTD_DISABLE) |
| 102 | return current; |
| 103 | |
| 104 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 105 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 106 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); |
| 107 | current += dmar->header.length; |
| 108 | current = acpi_align_current(current); |
| 109 | acpi_add_table(rsdp, dmar); |
| 110 | |
| 111 | return current; |
| 112 | } |