Mario Scheithauer | e27f654 | 2023-01-25 13:50:05 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <baseboard/variants.h> |
| 4 | #include <gpio.h> |
| 5 | #include <soc/meminit.h> |
| 6 | #include <soc/romstage.h> |
| 7 | |
| 8 | static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = { |
| 9 | |
| 10 | .dq_map[DDR_CH0] = { |
| 11 | {0xf, 0xf0}, |
| 12 | {0xf, 0xf0}, |
| 13 | {0xff, 0x0}, |
| 14 | {0x0, 0x0}, |
| 15 | {0x0, 0x0}, |
| 16 | {0x0, 0x0} |
| 17 | }, |
| 18 | |
| 19 | .dq_map[DDR_CH1] = { |
| 20 | {0xf, 0xf0}, |
| 21 | {0xf, 0xf0}, |
| 22 | {0xff, 0x0}, |
| 23 | {0x0, 0x0}, |
| 24 | {0x0, 0x0}, |
| 25 | {0x0, 0x0} |
| 26 | }, |
| 27 | |
| 28 | /* |
| 29 | * The dqs_map arrays map the ddr4 pins to the SoC pins |
| 30 | * for both channels. |
| 31 | * |
| 32 | * the index = pin number on ddr4 part |
| 33 | * the value = pin number on SoC |
| 34 | */ |
| 35 | .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, |
| 36 | .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, |
| 37 | |
| 38 | /* Baseboard uses 100, 100 and 100 rcomp resistors */ |
| 39 | .rcomp_resistor = {100, 100, 100}, |
| 40 | |
| 41 | .rcomp_targets = {60, 40, 30, 20, 30}, |
| 42 | |
| 43 | /* LPDDR4x does not allow interleaved memory */ |
| 44 | .dq_pins_interleaved = 0, |
| 45 | |
| 46 | /* Baseboard is using config 2 for vref_ca */ |
| 47 | .vref_ca_config = 2, |
| 48 | |
| 49 | /* Enable Early Command Training */ |
| 50 | .ect = 1, |
| 51 | |
| 52 | /* Set Board Type */ |
| 53 | .UserBd = BOARD_TYPE_MOBILE, |
| 54 | }; |
| 55 | |
| 56 | const struct mb_cfg *variant_memcfg_config(void) |
| 57 | { |
| 58 | return &mc_ehl_lpddr4x_memcfg_cfg; |
| 59 | } |