Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2019 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <fsp/api.h> |
| 19 | #include <fsp/util.h> |
| 20 | #include <intelblocks/acpi.h> |
| 21 | #include <intelblocks/cfg.h> |
| 22 | #include <intelblocks/itss.h> |
| 23 | #include <intelblocks/xdci.h> |
| 24 | #include <romstage_handoff.h> |
| 25 | #include <soc/intel/common/vbt.h> |
| 26 | #include <soc/itss.h> |
| 27 | #include <soc/pci_devs.h> |
| 28 | #include <soc/ramstage.h> |
| 29 | #include <soc/soc_chip.h> |
| 30 | |
| 31 | #if CONFIG(HAVE_ACPI_TABLES) |
| 32 | const char *soc_acpi_name(const struct device *dev) |
| 33 | { |
| 34 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 35 | return "PCI0"; |
| 36 | |
| 37 | if (dev->path.type != DEVICE_PATH_PCI) |
| 38 | return NULL; |
| 39 | |
| 40 | switch (dev->path.pci.devfn) { |
| 41 | case SA_DEVFN_ROOT: return "MCHC"; |
| 42 | case SA_DEVFN_IGD: return "GFX0"; |
| 43 | case PCH_DEVFN_ISH: return "ISHB"; |
| 44 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 45 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 46 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 47 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 48 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 49 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 50 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 51 | case PCH_DEVFN_CSE: return "CSE1"; |
| 52 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 53 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 54 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 55 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 56 | case PCH_DEVFN_SATA: return "SATA"; |
| 57 | case PCH_DEVFN_UART2: return "UAR2"; |
| 58 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 59 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 60 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 61 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 62 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 63 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 64 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 65 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 66 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 67 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 68 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 69 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 70 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 71 | case PCH_DEVFN_PCIE12: return "RP12"; |
| 72 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 73 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 74 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 75 | case PCH_DEVFN_PCIE16: return "RP16"; |
| 76 | case PCH_DEVFN_PCIE17: return "RP17"; |
| 77 | case PCH_DEVFN_PCIE18: return "RP18"; |
| 78 | case PCH_DEVFN_PCIE19: return "RP19"; |
| 79 | case PCH_DEVFN_PCIE20: return "RP20"; |
| 80 | case PCH_DEVFN_PCIE21: return "RP21"; |
| 81 | case PCH_DEVFN_PCIE22: return "RP22"; |
| 82 | case PCH_DEVFN_PCIE23: return "RP23"; |
| 83 | case PCH_DEVFN_PCIE24: return "RP24"; |
| 84 | case PCH_DEVFN_UART0: return "UAR0"; |
| 85 | case PCH_DEVFN_UART1: return "UAR1"; |
| 86 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 87 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 88 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 89 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 90 | case PCH_DEVFN_SDCARD: return "SDXC"; |
| 91 | /* Keeping ACPI device name coherent with ec.asl */ |
| 92 | case PCH_DEVFN_ESPI: return "LPCB"; |
| 93 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 94 | case PCH_DEVFN_PMC: return "PMC_"; |
| 95 | case PCH_DEVFN_HDA: return "HDAS"; |
| 96 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 97 | case PCH_DEVFN_SPI: return "FSPI"; |
| 98 | case PCH_DEVFN_GBE: return "IGBE"; |
| 99 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 100 | } |
| 101 | |
| 102 | return NULL; |
| 103 | } |
| 104 | #endif |
| 105 | |
| 106 | /* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ |
| 107 | static void soc_fill_gpio_pm_configuration(void) |
| 108 | { |
| 109 | uint8_t value[TOTAL_GPIO_COMM]; |
| 110 | const config_t *config = config_of_soc(); |
| 111 | |
| 112 | if (config->gpio_override_pm) |
| 113 | memcpy(value, config->gpio_pm, sizeof(uint8_t) * |
| 114 | TOTAL_GPIO_COMM); |
| 115 | else |
| 116 | memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * |
| 117 | TOTAL_GPIO_COMM); |
| 118 | |
| 119 | gpio_pm_configure(value, TOTAL_GPIO_COMM); |
| 120 | } |
| 121 | |
| 122 | void soc_init_pre_device(void *chip_info) |
| 123 | { |
| 124 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 125 | * default policy that doesn't honor boards' requirements. */ |
| 126 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 127 | |
| 128 | /* Perform silicon specific init. */ |
| 129 | fsp_silicon_init(romstage_handoff_is_resume()); |
| 130 | |
| 131 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 132 | fsp_display_fvi_version_hob(); |
| 133 | |
| 134 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 135 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 136 | |
| 137 | soc_fill_gpio_pm_configuration(); |
| 138 | } |
| 139 | |
| 140 | static void pci_domain_set_resources(struct device *dev) |
| 141 | { |
| 142 | assign_resources(dev->link_list); |
| 143 | } |
| 144 | |
| 145 | static struct device_operations pci_domain_ops = { |
| 146 | .read_resources = &pci_domain_read_resources, |
| 147 | .set_resources = &pci_domain_set_resources, |
| 148 | .scan_bus = &pci_domain_scan_bus, |
| 149 | #if CONFIG(HAVE_ACPI_TABLES) |
| 150 | .acpi_name = &soc_acpi_name, |
| 151 | #endif |
| 152 | }; |
| 153 | |
| 154 | static struct device_operations cpu_bus_ops = { |
| 155 | .read_resources = DEVICE_NOOP, |
| 156 | .set_resources = DEVICE_NOOP, |
| 157 | .enable_resources = DEVICE_NOOP, |
| 158 | .init = DEVICE_NOOP, |
| 159 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
| 160 | }; |
| 161 | |
| 162 | static void soc_enable(struct device *dev) |
| 163 | { |
| 164 | /* Set the operations if it is a special bus type */ |
| 165 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 166 | dev->ops = &pci_domain_ops; |
| 167 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 168 | dev->ops = &cpu_bus_ops; |
| 169 | } |
| 170 | |
| 171 | struct chip_operations soc_intel_tigerlake_ops = { |
| 172 | CHIP_NAME("Intel Tigerlake") |
| 173 | .enable_dev = &soc_enable, |
| 174 | .init = &soc_init_pre_device, |
| 175 | }; |