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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_XHCI_H
18#define _SOC_XHCI_H
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20/* XHCI PCI Registers */
21#define XHCI_PWR_CTL_STS 0x74
22#define XHCI_USB2PR 0xd0
23#define XHCI_USB2PRM 0xd4
24#define XHCI_USB3PR 0xd8
25#define XHCI_USB3PRM 0xdc
26#define XHCI_USB2PDO 0xe4
27#define XHCI_USB3PDO 0xe8
28
29/* XHCI Memory Registers */
30#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10))
31# define XHCI_USB3_PORTSC_CHST (0x7f << 17)
32# define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
33# define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
34# define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
35# define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
36# define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
Lee Leahy32471722015-04-20 15:20:28 -070037# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
Lee Leahy77ff0b12015-05-05 15:07:29 -070038# define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
39# define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
40# define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
41# define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
42# define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
43# define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */
44
Lee Leahy77ff0b12015-05-05 15:07:29 -070045#define XHCI_RESET_TIMEOUT 100000 /* 100ms */
46
Lee Leahy32471722015-04-20 15:20:28 -070047#endif /* _SOC_XHCI_H */