blob: 49f3fcc0ac1c196119afc528d104011d2d82f65f [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_SPI_H_
18#define _SOC_SPI_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20#include <stdint.h>
21
22/* These registers live behind SPI_BASE_ADDRESS. */
23#define HSFSTS 0x04
24#define FDATA0 0x10
25# define FLOCKDN (0x1 << 15)
26#define SSFS 0x90
27# define CYCLE_DONE_STATUS (0x1 << 2)
28# define FLASH_CYCLE_ERROR (0x1 << 3)
29#define SSFC 0x91
30# define SPI_CYCLE_GO (0x1 << 1)
31# define DATA_CYCLE (0x1 << 14)
32#define PREOP 0x94
33#define OPTYPE 0x96
34#define OPMENU0 0x98
35#define OPMENU1 0x9c
36#define LVSCC 0xc4
37# define VCL (0x1 << 23)
38# define EO(x) (((x) & 0xff) << 8)
39# define WG_1_BYTE (0x0 << 2)
40# define WG_64_BYTE (0x1 << 2)
41# define BES_256_BYTE (0x0 << 0)
42# define BES_4_KB (0x1 << 0)
43# define BES_8_KB (0x2 << 0)
44# define BES_64_KB (0x3 << 0)
45#define UVSCC 0xc8
46#define SCS 0xf8
47# define SMIWPEN (0x1 << 7)
48#define BCR 0xfc
49# define EISS (0x1 << 5)
50# define SRC_MASK (0x3 << 2)
51# define SRC_CACHE_NO_PREFETCH (0x0 << 2)
52# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2)
53# define SRC_CACHE_PREFETCH (0x2 << 2)
54# define BCR_LE (0x1 << 1)
55# define BCR_WPD (0x1 << 0)
56
57/*
58 * SPI lockdown configuration.
59 */
60struct spi_config {
61 uint16_t preop;
62 uint16_t optype;
63 uint32_t opmenu[2];
64 uint32_t lvscc;
65 uint32_t uvscc;
66};
67
68/* Return 0 on success < 0 on failure. */
69int mainboard_get_spi_config(struct spi_config *cfg);
70
Lee Leahy32471722015-04-20 15:20:28 -070071#endif /* _SOC_SPI_H_ */