blob: 9c6cb93f8a291eee3efafae3f22f2ed2cc3c3181 [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_SATA_H_
18#define _SOC_SATA_H_
19
20#define SATA_PORT_SUPPORT 0x03
21#define SATA_PORT_MASK 0x3f
22
23/* PCI Configuration Space */
24#define SATA_PID 0x70
25#define SATA_PID_NEXT 0xff00
26#define SATA_PID_CID 0xff
27
28#define SATA_MAP 0x90
29#define SATA_MAP_SPD3 (1 << 11)
30#define SATA_MAP_SPD2 (1 << 10)
31#define SATA_MAP_SPD1 (1 << 9)
32#define SATA_MAP_SPD0 (1 << 8)
33#define SATA_MAP_SPD_MASK (SATA_MAP_SPD0 | SATA_MAP_SPD1 \
34 | SATA_MAP_SPD2 | SATA_MAP_SPD3)
35#define SATA_MAP_SMS_RAID 0x40
36
37#define SATA_PCS 0x92
38#define SATA_PCS_ORM (1 << 15)
39#define SATA_PCS_PORT5 (1 << 5)
40#define SATA_PCS_PORT4 (1 << 4)
41#define SATA_PCS_PORT3 (1 << 3)
42#define SATA_PCS_PORT2 (1 << 2)
43#define SATA_PCS_PORT1 (1 << 1)
44#define SATA_PCS_PORT0 (1 << 0)
45#define SATA_PCS_PORTS (SATA_PCS_PORT0 | SATA_PCS_PORT1 | SATA_PCS_PORT2 \
46 | SATA_PCS_PORT3 | SATA_PCS_PORT4 | SATA_PCS_PORT5)
47
48#define SATA_TM 0x94
49#define SATA_TM_PCD5 (1 << 29)
50#define SATA_TM_PCD4 (1 << 28)
51#define SATA_TM_PCD3 (1 << 27)
52#define SATA_TM_PCD2 (1 << 26)
53#define SATA_TM_PCD1 (1 << 25)
54#define SATA_TM_PCD0 (1 << 24)
55#define SATA_TM_PCD_MASK (SATA_TM_PCD0 | SATA_TM_PCD1 | SATA_TM_PCD2 \
56 | SATA_TM_PCD3 | SATA_TM_PCD4 | SATA_TM_PCD5)
Lee Leahy77ff0b12015-05-05 15:07:29 -070057
58#define SATA_SIRI 0xa0
59#define SATA_SIRD 0xa4
60
Lee Leahy32471722015-04-20 15:20:28 -070061/* Memory Mapped I/O Space */
62#define AHCI_GHC_CAP 0
63#define AHCI_GHC_CAP_S64A (1 << 31)
64#define AHCI_GHC_CAP_SCQA (1 << 30)
65#define AHCI_GHC_CAP_SSNTF (1 << 29)
66#define AHCI_GHC_CAP_SMPS (1 << 28)
67#define AHCI_GHC_CAP_SSS (1 << 27)
68#define AHCI_GHC_CAP_SALP (1 << 26)
69#define AHCI_GHC_CAP_SAL (1 << 25)
70#define AHCI_GHC_CAP_SCLO (1 << 24)
71#define AHCI_GHC_CAP_ISS 0x00f00000
72#define AHCI_GHC_CAP_ISS_GEN1 (1 << 20)
73#define AHCI_GHC_CAP_ISS_GEN2 (2 << 20)
74#define AHCI_GHC_CAP_ISS_GEN3 (3 << 20)
75#define AHCI_GHC_CAP_SNZO (1 << 19)
76#define AHCI_GHC_CAP_SAM (1 << 18)
77#define AHCI_GHC_CAP_SMP (1 << 17)
78#define AHCI_GHC_CAP_FBSS (1 << 16)
79#define AHCI_GHC_CAP_PMD (1 << 15)
80#define AHCI_GHC_CAP_SSC (1 << 14)
81#define AHCI_GHC_CAP_PSC (1 << 13)
82#define AHCI_GHC_CAP_NCS 0x00000f00
83#define AHCI_GHC_CAP_CCCS (1 << 7)
84#define AHCI_GHC_CAP_EMS (1 << 6)
85#define AHCI_GHC_CAP_SXS (1 << 5)
86#define AHCI_GHC_CAP_NP 0x0000001f
87
88#define AHCI_HBA_CTRL 4
89#define AHCI_HBA_CTRL_AE (1 << 31)
90#define AHCI_HBA_CTRL_MRSM (1 << 2)
91#define AHCI_HBA_CTRL_IE (1 << 1)
92#define AHCI_HBA_CTRL_HR (1 << 0)
93
94#define AHCI_GHC_PI 0x000c
95#define AHCI_GHC_CAP2 0x0024
96#define AHCI_GHC_CAP2_DESO (1 << 5)
97#define AHCI_GHC_CAP2_SADM (1 << 4)
98#define AHCI_GHC_CAP2_SDS (1 << 3)
99#define AHCI_GHC_CAP2_APST (1 << 2)
100#define AHCI_GHC_CAP2_BOH (1 << 0)
101
102#define AHCI_VSP 0x00a0
103#define AHCI_VSP_SFMS (1 << 6)
104#define AHCI_VSP_PFS (1 << 5)
105#define AHCI_VSP_PT (1 << 4)
106#define AHCI_VSP_SRPIR (1 << 3)
107
108#define AHCI_SFM 0xc8
109#define AHCI_SFM_OROM_UI 0x0c00
110#define AHCI_SFM_OROM_UI_2SEC 0
111#define AHCI_SFM_OROM_UI_4SEC (1 << 10)
112#define AHCI_SFM_OROM_UI_6SEC (2 << 10)
113#define AHCI_SFM_OROM_UI_8SEC (3 << 10)
114#define AHCI_SFM_SRT (1 << 9)
115#define AHCI_SFM_RRT_ESATA (1 << 8)
116#define AHCI_SFM_LED (1 << 7)
117#define AHCI_SFM_HDDUNLOCK (1 << 6)
118#define AHCI_SFM_OROM_UI_BANNER (1 << 5)
119#define AHCI_SFM_RRT (1 << 4)
120#define AHCI_SFM_R5 (1 << 3)
121#define AHCI_SFM_R10 (1 << 2)
122#define AHCI_SFM_R1 (1 << 1)
123#define AHCI_SFM_R0 (1 << 0)
124
125#define AHCI_PXCMD0 0x0118
126#define AHCI_PXCMD1 0x0198
127
128#define AHCI_PXCMD_ICC 0xf0000000
129#define AHCI_PXCMD_ASP (1 << 27)
130#define AHCI_PXCMD_ALPE (1 << 26)
131#define AHCI_PXCMD_DLAE (1 << 25)
132#define AHCI_PXCMD_ATAPI (1 << 24)
133#define AHCI_PXCMD_APSTE (1 << 23)
134#define AHCI_PXCMD_FBSCP (1 << 22)
135#define AHCI_PXCMD_ESP (1 << 21)
136#define AHCI_PXCMD_CPD (1 << 20)
137#define AHCI_PXCMD_MPSP (1 << 19)
138#define AHCI_PXCMD_HPCP (1 << 18)
139#define AHCI_PXCMD_PMA (1 << 17)
140#define AHCI_PXCMD_CR (1 << 15)
141#define AHCI_PXCMD_FR (1 << 14)
142#define AHCI_PXCMD_MPSS (1 << 13)
143#define AHCI_PXCMD_CCS 0x00001f00
144#define AHCI_PXCMD_PSP (1 << 6)
145#define AHCI_PXCMD_FRE (1 << 4)
146#define AHCI_PXCMD_CLO (1 << 3)
147#define AHCI_PXCMD_POD (1 << 2)
148#define AHCI_PXCMD_SUD (1 << 1)
149#define AHCI_PXCMD_ST (1 << 0)
150
151#endif /* _SOC_SATA_H_ */