blob: 5ac29f4e307dfb7b1b2cc6fa0de6ae80ec3810f2 [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahyb092c9e2016-01-01 18:09:50 -08005 * Copyright (C) 2015-2016 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_PM_H_
18#define _SOC_PM_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
Stefan Reinauer6a001132017-07-13 02:20:27 +020020#include <compiler.h>
Aaron Durbin1b6196d2016-07-13 23:20:26 -050021#include <arch/acpi.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070022
23#define IOCOM1 0x3f8
24
25/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
26#define PRSTS 0x00
27# define PMC_WDT_STS (1 << 15)
28# define SEC_GBLRST_STS (1 << 7)
29# define SEC_WDT_STS (1 << 6)
30# define WOL_OVR_WK_STS (1 << 5)
31# define PMC_WAKE_STS (1 << 4)
32#define PMC_CFG 0x08
33# define SPS (1 << 5)
34# define NO_REBOOT (1 << 4)
35# define SX_ENT_TO_EN (1 << 3)
36# define TIMING_T581_SHIFT (0)
37# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT)
38# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT)
39# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT)
40# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT)
41# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT)
42#define VLV_PM_STS 0x0c
43# define PMC_MSG_FULL_STS (1 << 24)
44# define PMC_MSG_4_FULL_STS (1 << 23)
45# define PMC_MSG_3_FULL_STS (1 << 22)
46# define PMC_MSG_2_FULL_STS (1 << 21)
47# define PMC_MSG_1_FULL_STS (1 << 20)
48# define CODE_REQ (1 << 8)
49# define HPR_ENT_TO (1 << 2)
50# define SX_ENT_TO (1 << 1)
51#define GEN_PMCON1 0x20
52# define UART_EN (1 << 24)
53# define DISB (1 << 23)
54# define MEM_SR (1 << 21)
55# define SRS (1 << 20)
56# define CTS (1 << 19)
57# define MS4V (1 << 18)
58# define PWR_FLR (1 << 16)
59# define PME_B0_S5_DIS (1 << 15)
60# define SUS_PWR_FLR (1 << 14)
61# define WOL_EN_OVRD (1 << 13)
62# define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
63# define GEN_RST_STS (1 << 9)
64# define RPS (1 << 2)
65# define AFTERG3_EN (1 << 0)
66#define GEN_PMCON2 0x24
67# define SLPSX_STR_POL_LOCK (1 << 18)
68# define BIOS_PCI_EXP_EN (1 << 10)
69# define PWRBTN_LVL (1 << 9)
70# define SMI_LOCK (1 << 4)
71#define ETR 0x48
72# define CF9LOCK (1 << 31)
73# define LTR_DEF (1 << 22)
74# define IGNORE_HPET (1 << 21)
75# define CF9GR (1 << 20)
76# define CWORWRE (1 << 18)
77#define FUNC_DIS 0x34
78# define SIO_DMA2_DIS (1 << 0)
79# define PWM1_DIS (1 << 1)
80# define PWM2_DIS (1 << 2)
81# define HSUART1_DIS (1 << 3)
82# define HSUART2_DIS (1 << 4)
83# define SPI_DIS (1 << 5)
84# define SDIO_DIS (1 << 9)
85# define SD_DIS (1 << 10)
86# define MMC_DIS (1 << 11)
87# define HDA_DIS (1 << 12)
88# define LPE_DIS (1 << 13)
89# define OTG_DIS (1 << 14)
90# define XHCI_DIS (1 << 15)
91# define SATA_DIS (1 << 17)
92# define EHCI_DIS (1 << 18)
93# define TXE_DIS (1 << 19)
94# define PCIE_PORT1_DIS (1 << 20)
95# define PCIE_PORT2_DIS (1 << 21)
96# define PCIE_PORT3_DIS (1 << 22)
97# define PCIE_PORT4_DIS (1 << 23)
98# define SIO_DMA1_DIS (1 << 24)
99# define I2C1_DIS (1 << 25)
100# define I2C2_DIS (1 << 26)
101# define I2C3_DIS (1 << 27)
102# define I2C4_DIS (1 << 28)
103# define I2C5_DIS (1 << 29)
104# define I2C6_DIS (1 << 30)
105# define I2C7_DIS (1 << 31)
106#define FUNC_DIS2 0x38
107# define USH_SS_PHY_DIS (1 << 2)
108# define OTG_SS_PHY_DIS (1 << 1)
109# define SMBUS_DIS (1 << 0)
110#define GPIO_ROUT 0x58
111# define ROUTE_MASK 3
112# define ROUTE_NONE 0
113# define ROUTE_SMI 1
114# define ROUTE_SCI 2
115#define PLT_CLK_CTL_0 0x60
116#define PLT_CLK_CTL_1 0x64
117#define PLT_CLK_CTL_2 0x68
118#define PLT_CLK_CTL_3 0x6c
119#define PLT_CLK_CTL_4 0x70
120#define PLT_CLK_CTL_5 0x74
fdurairxaff502e2015-08-21 15:36:53 -0700121# define CLK_SRC_XTAL (0x0 << 2)
122# define CLK_SRC_PLL (0x1 << 2)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700123# define CLK_CTL_D3_LPE (0x0 << 0)
124# define CLK_CTL_ON (0x1 << 0)
125# define CLK_CTL_OFF (0x2 << 0)
126#define PME_STS 0xc0
127#define GPE_LEVEL_EDGE 0xc4
128# define GPE_EDGE 0
129# define GPE_LEVEL 1
130#define GPE_POLARITY 0xc8
131# define GPE_ACTIVE_HIGH 1
132# define GPE_ACTIVE_LOW 0
133#define LOCK 0xcc
134
135/* IO Mapped registers behind ACPI_BASE_ADDRESS */
136#define PM1_STS 0x00
137#define WAK_STS (1 << 15)
138#define PCIEXPWAK_STS (1 << 14)
139#define USB_STS (1 << 13)
140#define PRBTNOR_STS (1 << 11)
141#define RTC_STS (1 << 10)
142#define PWRBTN_STS (1 << 8)
143#define GBL_STS (1 << 5)
144#define TMROF_STS (1 << 0)
145#define PM1_EN 0x02
146#define PCIEXPWAK_DIS (1 << 14)
147#define USB_WAKE_EN (1 << 13)
148#define RTC_EN (1 << 10)
149#define PWRBTN_EN (1 << 8)
150#define GBL_EN (1 << 5)
151#define TMROF_EN (1 << 0)
152#define PM1_CNT 0x04
Lee Leahy77ff0b12015-05-05 15:07:29 -0700153#define GBL_RLS (1 << 2)
154#define BM_RLD (1 << 1)
155#define SCI_EN (1 << 0)
156#define PM1_TMR 0x08
157#define GPE0_STS 0x20
Lee Leahy77ff0b12015-05-05 15:07:29 -0700158#define GPE0_EN 0x28
Lee Leahy77ff0b12015-05-05 15:07:29 -0700159#define SUS_GPIO_EN7_BIT 23
160#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT)
161#define SUS_GPIO_EN6_BIT 22
162#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT)
163#define SUS_GPIO_EN5_BIT 21
164#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT)
165#define SUS_GPIO_EN4_BIT 20
166#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT)
167#define SUS_GPIO_EN3_BIT 19
168#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT)
169#define SUS_GPIO_EN2_BIT 18
170#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT)
171#define SUS_GPIO_EN1_BIT 17
172#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT)
173#define SUS_GPIO_EN0_BIT 16
174#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT)
Lee Leahy32471722015-04-20 15:20:28 -0700175#define SUS_GPIO_STS0 (1 << 16)
176#define PCIE_WAKE3_STS (1 << 8)
177#define PCIE_WAKE2_STS (1 << 7)
178#define PCIE_WAKE1_STS (1 << 6)
179#define PCIE_WAKE0_STS (1 << 3)
180#define PCI_EXP_STS (1 << 9)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700181#define PME_B0_EN (1 << 13)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700182#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT
183#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x)
184#define SMI_EN 0x30
Lee Leahy32471722015-04-20 15:20:28 -0700185#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
186#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */
187#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
188#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
189#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
190#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
191#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
192#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */
193#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
194#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
195#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700196#define SMI_STS 0x34
197#define ALT_GPIO_SMI 0x38
198#define UPRWC 0x3c
Lee Leahy32471722015-04-20 15:20:28 -0700199# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700200#define GPE_CTRL 0x40
201#define PM2A_CNT_BLK 0x50
202#define TCO_RLD 0x60
203#define TCO_STS 0x64
204# define SECOND_TO_STS (1 << 17)
205# define TCO_TIMEOUT (1 << 3)
206#define TCO1_CNT 0x68
207# define TCO_LOCK (1 << 12)
208# define TCO_TMR_HALT (1 << 11)
209#define TCO_TMR 0x70
210
Lee Leahy77ff0b12015-05-05 15:07:29 -0700211#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
212
213/* Track power state from reset to log events. */
214struct chipset_power_state {
215 uint16_t pm1_sts;
216 uint16_t pm1_en;
217 uint32_t pm1_cnt;
218 uint32_t gpe0_sts;
219 uint32_t gpe0_en;
220 uint32_t tco_sts;
221 uint32_t prsts;
222 uint32_t gen_pmcon1;
223 uint32_t gen_pmcon2;
Lee Leahy32471722015-04-20 15:20:28 -0700224 int prev_sleep_state;
Stefan Reinauer6a001132017-07-13 02:20:27 +0200225} __packed;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700226
Lee Leahyb092c9e2016-01-01 18:09:50 -0800227struct chipset_power_state *fill_power_state(void);
228
Lee Leahy77ff0b12015-05-05 15:07:29 -0700229/* Power Management Utility Functions. */
230uint16_t get_pmbase(void);
231uint32_t clear_smi_status(void);
232uint16_t clear_pm1_status(void);
233uint32_t clear_tco_status(void);
234uint32_t clear_gpe_status(void);
235uint32_t clear_alt_status(void);
236void clear_pmc_status(void);
237void enable_smi(uint32_t mask);
238void disable_smi(uint32_t mask);
239void enable_pm1(uint16_t events);
240void enable_pm1_control(uint32_t mask);
241void disable_pm1_control(uint32_t mask);
242void enable_gpe(uint32_t mask);
243void disable_gpe(uint32_t mask);
244void disable_all_gpe(void);
245
Lee Leahy32471722015-04-20 15:20:28 -0700246#if IS_ENABLED(CONFIG_ELOG)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700247void southcluster_log_state(void);
248#else
249static inline void southcluster_log_state(void) {}
250#endif
251
Aaron Durbinb19e33f2017-09-15 14:32:13 -0600252/* Return non-zero when RTC failure happened. */
253int rtc_failure(void);
254
Lee Leahy77ff0b12015-05-05 15:07:29 -0700255#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
256
Lee Leahy32471722015-04-20 15:20:28 -0700257#endif /* _SOC_PM_H_ */