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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google, Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
Marshall Dawsone8c527e2017-01-13 14:23:49 -070012 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Lee Leahy77ff0b12015-05-05 15:07:29 -070013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_PCIE_H_
18#define _SOC_PCIE_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20/* PCIe root port config space registers. */
21#define XCAP 0x40
22# define SI (1 << 24)
23#define DCAP 0x44
24# define MPS_MASK 0x7
25#define DCTL_DSTS 0x48
26# define URE (1 << 3)
27# define FEE (1 << 2)
28# define NFE (1 << 1)
29# define CEE (1 << 0)
30#define LCAP 0x4c
31# define L1EXIT_SHIFT 15
32# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT)
33#define LCTL 0x50
34# define CCC (1 << 6)
35# define RL (1 << 5)
36# define LD (1 << 4)
37#define LSTS 0x52
38#define SLCAP 0x54
39# define SLN_SHIFT 19
40# define SLS_SHIFT 15
41# define SLV_SHIFT 7
42# define HPC (1 << 6)
43# define HPS (1 << 5)
44#define SLCTL_SLSTS 0x58
45# define PDS (1 << 22)
46#define DCAP2 0x64
47# define OBFFS (0x3 << 18)
48# define LTRMS (1 << 11)
49#define DSTS2 0x68
50# define OBFFEN (3 << 13)
51# define LTRME (1 << 10)
52# define CTD (1 << 4)
53#define CHCFG 0xd0
54# define UPSD (1 << 24)
55# define UNRS (1 << 15)
56# define UPRS (1 << 14)
57#define MPC2 0xd4
58# define IPF (1 << 11)
59# define LSTP (1 << 6)
60# define EOIFD (1 << 1)
61#define MPC 0xd8
62# define CCEL_SHIFT 15
63# define CCEL_MASK (0x7 << CCEL_SHIFT)
64#define RPPGEN 0xe0
65# define RPSCGEN (1 << 15)
66# define LCLKREQEN (1 << 13)
67# define BBCLKREQEN (1 << 12)
68# define SRDLCGEN (1 << 11)
69# define SRDBCGEN (1 << 10)
70# define RPDLCGEN (1 << 9)
71# define RPDBCGEN (1 << 8)
72#define PWRCTL 0xe8
73# define RPL1SQPOL (1 << 1)
74# define RPDTSQPOL (1 << 0)
75#define PHYCTL2_IOSFBCTL 0xf4
76# define PLL_OFF_EN (1 << 8)
77# define TDFT (3 << 14)
78# define TXCFGCHWAIT (3 << 12)
79# define SIID (3 << 26)
80#define STRPFUSECFG 0xfc
81# define LANECFG_SHIFT 14
82# define LANECFG_MASK (0x3 << LANECFG_SHIFT)
83#define AERCH 0x100
84#define NFTS 0x314
85#define L0SC 0x318
86#define CFG2 0x320
87# define CSREN (1 << 22)
88# define LATGC_SHIFT 6
89# define LATGC_MASK (0x7 << LATGC_SHIFT)
90#define PCIEDBG 0x324
91# define SPCE (1 << 5)
92#define PCIESTS1 0x328
93#define PCIEALC 0x338
94#define RTP 0x33c
95#define PHYCTL4 0x408
96# define SQDIS (1 << 27)
97
Lee Leahy32471722015-04-20 15:20:28 -070098#endif /* _SOC_PCIE_H_ */