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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google, Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
Marshall Dawsone8c527e2017-01-13 14:23:49 -070012 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Lee Leahy77ff0b12015-05-05 15:07:29 -070013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_MSR_H_
18#define _SOC_MSR_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20#define MSR_IA32_PLATFORM_ID 0x17
Lee Leahy32471722015-04-20 15:20:28 -070021#define MSR_IA32_BIOS_SIGN_ID 0x8B
Lee Leahy77ff0b12015-05-05 15:07:29 -070022#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
23#define MSR_PLATFORM_INFO 0xce
24#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
Lee Leahy32471722015-04-20 15:20:28 -070025#define SINGLE_PCTL (1 << 11)
Lee Leahy77ff0b12015-05-05 15:07:29 -070026#define MSR_POWER_MISC 0x120
Lee Leahy32471722015-04-20 15:20:28 -070027#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
28#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
Lee Leahy77ff0b12015-05-05 15:07:29 -070029#define MSR_IA32_PERF_CTL 0x199
30#define MSR_IA32_MISC_ENABLES 0x1a0
31#define MSR_POWER_CTL 0x1fc
32#define MSR_PKG_POWER_SKU_UNIT 0x606
33#define MSR_PKG_POWER_LIMIT 0x610
34#define MSR_PP1_POWER_LIMIT 0x638
35#define MSR_IACORE_RATIOS 0x66a
36#define MSR_IACORE_TURBO_RATIOS 0x66c
37#define MSR_IACORE_VIDS 0x66b
38#define MSR_IACORE_TURBO_VIDS 0x66d
39#define MSR_PKG_TURBO_CFG1 0x670
40#define MSR_CPU_TURBO_WKLD_CFG1 0x671
41#define MSR_CPU_TURBO_WKLD_CFG2 0x672
42#define MSR_CPU_THERM_CFG1 0x673
43#define MSR_CPU_THERM_CFG2 0x674
44#define MSR_CPU_THERM_SENS_CFG 0x675
45
Subrata Banik45a221d2015-08-05 17:01:55 +053046/* Read BCLK from MSR */
47unsigned int cpu_bus_freq_khz(void);
Lee Leahy77ff0b12015-05-05 15:07:29 -070048
Lee Leahy32471722015-04-20 15:20:28 -070049#endif /* _SOC_MSR_H_ */