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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_LPC_H_
18#define _SOC_LPC_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20/* PCI config registers in LPC bridge. */
21#define REVID 0x08
22#define ABASE 0x40
23#define PBASE 0x44
24#define GBASE 0x48
25#define IOBASE 0x4c
26#define IBASE 0x50
27#define SBASE 0x54
28#define MPBASE 0x58
29#define PUBASE 0x5c
30#define UART_CONT 0x80
31#define RCBA 0xf0
32
Hannah Williams3fa80a92017-03-22 16:33:36 -070033/* Memory Mapped IO in LPC bridge */
34#define SCNT 0x10
35#define SCNT_MODE (1 << 7) /* When cleared, SERIRQ is in quiet mode */
Lee Leahy77ff0b12015-05-05 15:07:29 -070036
37#define RID_A_STEPPING_START 1
38#define RID_B_STEPPING_START 5
39#define RID_C_STEPPING_START 0xe
Lee Leahy32471722015-04-20 15:20:28 -070040enum soc_stepping {
Lee Leahy77ff0b12015-05-05 15:07:29 -070041 STEP_A0,
42 STEP_A1,
43 STEP_B0,
44 STEP_B1,
45 STEP_B2,
46 STEP_B3,
47 STEP_C0,
48};
49
50/* Registers behind the RCBA_BASE_ADDRESS bar. */
51#define GCS 0x00
52# define BILD (1 << 0)
53
Lee Leahy32471722015-04-20 15:20:28 -070054#endif /* _SOC_LPC_H_ */