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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google, Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
Marshall Dawsone8c527e2017-01-13 14:23:49 -070012 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Lee Leahy77ff0b12015-05-05 15:07:29 -070013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_IOSF_H_
18#define _SOC_IOSF_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
Lee Leahyacb9c0b2015-07-02 11:55:18 -070020#include <rules.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070021#include <stdint.h>
Lee Leahy32471722015-04-20 15:20:28 -070022#if ENV_RAMSTAGE
23#include <device/device.h>
24#include <reg_script.h>
25#endif /* ENV_RAMSTAGE */
Lee Leahy77ff0b12015-05-05 15:07:29 -070026#include <soc/pci_devs.h>
27
28/*
Lee Leahy32471722015-04-20 15:20:28 -070029 * The SoC has a message network called IOSF Sideband. The access
Lee Leahy77ff0b12015-05-05 15:07:29 -070030 * routines are through 3 registers in PCI config space of 00:00.0:
31 * MCR - control register
32 * MDR - data register
33 * MCRX - control register extension
Lee Leahy32471722015-04-20 15:20:28 -070034 * The extension register is only used for addresses that don't fit
35 * into the 8 bit register address.
Lee Leahy77ff0b12015-05-05 15:07:29 -070036 */
37
38#ifndef PCI_DEV
39#define PCI_DEV(SEGBUS, DEV, FN) ( \
Lee Leahy32471722015-04-20 15:20:28 -070040 (((SEGBUS) & 0xFFF) << 20) | \
41 (((DEV) & 0x1F) << 15) | \
42 (((FN) & 0x07) << 12))
Lee Leahy77ff0b12015-05-05 15:07:29 -070043#endif
Lee Leahy32471722015-04-20 15:20:28 -070044#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC)
Lee Leahy77ff0b12015-05-05 15:07:29 -070045
46#define MCR_REG 0xd0
47#define IOSF_OPCODE(x) ((x) << 24)
48#define IOSF_PORT(x) ((0xff & (x)) << 16)
49#define IOSF_REG(x) ((0xff & (x)) << 8)
50#define IOSF_REG_UPPER(x) (((~0xff) & (x)))
51#define IOSF_BYTE_EN_0 0x10
52#define IOSF_BYTE_EN_1 0x20
53#define IOSF_BYTE_EN_2 0x40
54#define IOSF_BYTE_EN_3 0x80
55#define IOSF_BYTE_EN \
56 (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3)
57#define MDR_REG 0xd4
58#define MCRX_REG 0xd8
59
Lee Leahy77ff0b12015-05-05 15:07:29 -070060uint32_t iosf_bunit_read(int reg);
61void iosf_bunit_write(int reg, uint32_t val);
Lee Leahy77ff0b12015-05-05 15:07:29 -070062uint32_t iosf_punit_read(int reg);
63void iosf_punit_write(int reg, uint32_t val);
Lee Leahy77ff0b12015-05-05 15:07:29 -070064uint32_t iosf_score_read(int reg);
65void iosf_score_write(int reg, uint32_t val);
Lee Leahy32471722015-04-20 15:20:28 -070066uint32_t iosf_lpss_read(int reg);
67void iosf_lpss_write(int reg, uint32_t val);
68uint32_t iosf_port58_read(int reg);
69void iosf_port58_write(int reg, uint32_t val);
Lee Leahy77ff0b12015-05-05 15:07:29 -070070uint32_t iosf_scc_read(int reg);
71void iosf_scc_write(int reg, uint32_t val);
shkimcc728f02015-09-22 17:53:58 +090072uint32_t iosf_usbphy_read(int reg);
73void iosf_usbphy_write(int reg, uint32_t val);
Lee Leahy32471722015-04-20 15:20:28 -070074
75#if ENV_RAMSTAGE
76uint64_t reg_script_read_iosf(struct reg_script_context *ctx);
77void reg_script_write_iosf(struct reg_script_context *ctx);
78#endif /* ENV_RAMSTAGE */
Lee Leahy77ff0b12015-05-05 15:07:29 -070079
80/* IOSF ports. */
81#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */
Lee Leahy77ff0b12015-05-05 15:07:29 -070082#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */
83#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */
84#define IOSF_PORT_PMC 0x04 /* Power Management Controller */
Lee Leahy77ff0b12015-05-05 15:07:29 -070085#define IOSF_PORT_SEC 0x44 /* SEC */
86#define IOSF_PORT_0x45 0x45
87#define IOSF_PORT_0x46 0x46
88#define IOSF_PORT_0x47 0x47
89#define IOSF_PORT_SCORE 0x48 /* SCORE */
90#define IOSF_PORT_0x55 0x55
91#define IOSF_PORT_0x58 0x58
92#define IOSF_PORT_0x59 0x59
93#define IOSF_PORT_0x5a 0x5a
94#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */
95#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */
shkimcc728f02015-09-22 17:53:58 +090096#define IOSF_PORT_USBPHY 0x43 /* USB PHY */
Lee Leahy77ff0b12015-05-05 15:07:29 -070097#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */
98#define IOSF_PORT_0xa2 0xa2
Lee Leahy77ff0b12015-05-05 15:07:29 -070099#define IOSF_PORT_SSUS 0xa8 /* SUS */
100#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */
101
102/* Read and write opcodes differ per port. */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700103#define IOSF_OP_READ_BUNIT 0x10
104#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1)
105#define IOSF_OP_READ_PMC 0x06
106#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700107#define IOSF_OP_READ_SCORE 0x06
108#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700109#define IOSF_OP_READ_LPSS 0x06
110#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1)
Lee Leahy32471722015-04-20 15:20:28 -0700111#define IOSF_OP_READ_0x58 0x06
112#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1)
113#define IOSF_OP_READ_SCC 0x06
114#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1)
shkimcc728f02015-09-22 17:53:58 +0900115#define IOSF_OP_READ_USBPHY 0x06
116#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700117
118/*
119 * BUNIT Registers.
120 */
121
Lee Leahy77ff0b12015-05-05 15:07:29 -0700122/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
123#define BUNIT_BMBOUND 0x25
Lee Leahy32471722015-04-20 15:20:28 -0700124/*
Elyes HAOUAS038e7242016-07-29 18:31:16 +0200125 * BMBOUND_HI describes the available RAM above 4GiB. It has a
Lee Leahy77ff0b12015-05-05 15:07:29 -0700126 * 256MiB granularity. Physical address bits 35:28 are compared with 31:24
127 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
128 * granularity care needs to be taken with the e820 map to account for a hole
Elyes HAOUAS038e7242016-07-29 18:31:16 +0200129 * in the RAM.
Lee Leahy32471722015-04-20 15:20:28 -0700130 */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700131#define BUNIT_BMBOUND_HI 0x26
132#define BUNIT_MMCONF_REG 0x27
Lee Leahy32471722015-04-20 15:20:28 -0700133#define BUNIT_BMISC 0x28
Lee Leahy77ff0b12015-05-05 15:07:29 -0700134/* The SMMRR registers define the SMM region in MiB granularity. */
Chiranjeevi Rapolufd016a42015-08-11 14:09:46 -0700135#define BUNIT_SMRWAC 0x2d
Lee Leahy77ff0b12015-05-05 15:07:29 -0700136#define BUNIT_SMRRL 0x2e
137#define BUNIT_SMRRH 0x2f
Lee Leahy77ff0b12015-05-05 15:07:29 -0700138
Chiranjeevi Rapolufd016a42015-08-11 14:09:46 -0700139/* SA ID bits. */
140#define SAI_IA_UNTRUSTED (1 << 0)
141#define SAI_IA_SMM (1 << 2)
142#define SAI_IA_BOOT (1 << 4)
143
Lee Leahy77ff0b12015-05-05 15:07:29 -0700144/*
145 * LPSS Registers
146 */
147#define LPSS_SIO_DMA1_CTL 0x280
148#define LPSS_I2C1_CTL 0x288
149#define LPSS_I2C2_CTL 0x290
150#define LPSS_I2C3_CTL 0x298
151#define LPSS_I2C4_CTL 0x2a0
152#define LPSS_I2C5_CTL 0x2a8
153#define LPSS_I2C6_CTL 0x2b0
154#define LPSS_I2C7_CTL 0x2b8
155#define LPSS_SIO_DMA2_CTL 0x240
156#define LPSS_PWM1_CTL 0x248
157#define LPSS_PWM2_CTL 0x250
158#define LPSS_HSUART1_CTL 0x258
159#define LPSS_HSUART2_CTL 0x260
160#define LPSS_SPI_CTL 0x268
161# define LPSS_CTL_ACPI_INT_EN (1 << 21)
162# define LPSS_CTL_PCI_CFG_DIS (1 << 20)
163# define LPSS_CTL_SNOOP (1 << 18)
164# define LPSS_CTL_NOSNOOP (1 << 19)
165# define LPSS_CTL_PM_CAP_PRSNT (1 << 1)
166
167/*
168 * SCC Registers
169 */
170#define SCC_SD_CTL 0x504
171#define SCC_SDIO_CTL 0x508
Lee Leahy32471722015-04-20 15:20:28 -0700172#define SCC_MMC_CTL 0x500
Lee Leahy77ff0b12015-05-05 15:07:29 -0700173# define SCC_CTL_PCI_CFG_DIS (1 << 0)
174# define SCC_CTL_ACPI_INT_EN (1 << 1)
175
176/*
Lee Leahy77ff0b12015-05-05 15:07:29 -0700177 * LPE Registers
178 */
179#define LPE_PCICFGCTR1 0x0500
180# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0)
181# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1)
182
Lee Leahy32471722015-04-20 15:20:28 -0700183/*
shkimcc728f02015-09-22 17:53:58 +0900184 * USBPHY Registers
185 */
186#define USBPHY_COMPBG 0x7f04
187
188/*
Lee Leahy32471722015-04-20 15:20:28 -0700189 * IO Sideband Function
190 */
191
192#if ENV_RAMSTAGE
193#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
194 _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
195 REG_SCRIPT_TYPE_IOSF, \
196 REG_SCRIPT_SIZE_32, \
197 reg_, mask_, value_, timeout_, unit_)
198#define REG_IOSF_READ(unit_, reg_) \
199 REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
200#define REG_IOSF_WRITE(unit_, reg_, value_) \
201 REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
202#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
203 REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
204#define REG_IOSF_OR(unit_, reg_, value_) \
205 REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
206#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
207 REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
208#endif /* ENV_RAMSTAGE */
209
210#endif /* _SOC_IOSF_H_ */