blob: 5a516203331abf5905d07d22018cf03bf18c9c83 [file] [log] [blame]
Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#ifndef _SOC_GFX_H_
18#define _SOC_GFX_H_
Lee Leahy77ff0b12015-05-05 15:07:29 -070019
20/*
21 * PCI config registers.
22 */
23
24#define GGC 0x50
Lee Leahy32471722015-04-20 15:20:28 -070025# define GGC_VAMEN (1 << 14) /* Enable acceleration mode */
26# define GGC_GTT_SIZE_MASK (3 << 8) /* GTT graphics memory size */
Lee Leahy77ff0b12015-05-05 15:07:29 -070027# define GGC_GTT_SIZE_0MB (0 << 8)
Lee Leahy32471722015-04-20 15:20:28 -070028# define GGC_GTT_SIZE_2MB (1 << 8)
29# define GGC_GTT_SIZE_4MB (2 << 8)
30# define GGC_GTT_SIZE_8MB (3 << 8)
31# define GGC_GSM_SIZE_MASK (0x1f << 3) /* Main memory use */
Lee Leahy77ff0b12015-05-05 15:07:29 -070032# define GGC_GSM_SIZE_0MB (0 << 3)
33# define GGC_GSM_SIZE_32MB (1 << 3)
34# define GGC_GSM_SIZE_64MB (2 << 3)
Lee Leahy32471722015-04-20 15:20:28 -070035# define GCC_GSM_SIZE_96MB (3 << 3)
Lee Leahy77ff0b12015-05-05 15:07:29 -070036# define GGC_GSM_SIZE_128MB (4 << 3)
Lee Leahy32471722015-04-20 15:20:28 -070037# define GGC_GSM_SIZE_160MB (5 << 3)
38# define GGC_GSM_SIZE_192MB (6 << 3)
39# define GGC_GSM_SIZE_224MB (7 << 3)
40# define GGC_GSM_SIZE_256MB (8 << 3)
41# define GGC_GSM_SIZE_288MB (9 << 3)
42# define GGC_GSM_SIZE_320MB (0x0a << 3)
43# define GGC_GSM_SIZE_352MB (0x0b << 3)
44# define GGC_GSM_SIZE_384MB (0x0c << 3)
45# define GGC_GSM_SIZE_416MB (0x0d << 3)
46# define GGC_GSM_SIZE_448MB (0x0e << 3)
47# define GGC_GSM_SIZE_480MB (0x0f << 3)
48# define GGC_GSM_SIZE_512MB (0x10 << 3)
49# define GGC_VGA_DISABLE (1 << 1) /* VGA Disable */
50# define GGC_GGCLCK (1 << 0) /* Prevent register writes */
Lee Leahy77ff0b12015-05-05 15:07:29 -070051
52#define GSM_BASE 0x5c
Lee Leahy32471722015-04-20 15:20:28 -070053# define GSM_BDSM 0xfff00000 /* Base of stolen memory */
54# define GSM_BDSM_LOCK (1 << 0) /* Prevent register writes */
55
Lee Leahy77ff0b12015-05-05 15:07:29 -070056#define GTT_BASE 0x70
Lee Leahy32471722015-04-20 15:20:28 -070057# define GTT_BGSM 0xfff00000 /* Base of stolen memory */
58# define GTT_BGSM_LOCK (1 << 0) /* Prevent register writes */
Lee Leahy77ff0b12015-05-05 15:07:29 -070059
60#define MSAC 0x62
61#define APERTURE_SIZE_MASK (3 << 1)
62#define APERTURE_SIZE_128MB (0 << 1)
63#define APERTURE_SIZE_256MB (1 << 1)
64#define APERTURE_SIZE_512MB (3 << 1)
65
Lee Leahy32471722015-04-20 15:20:28 -070066#define SWSCI 0xe8 /* SWSCI enable */
67#define ASLS 0xfc /* OpRegion Base */
Lee Leahy77ff0b12015-05-05 15:07:29 -070068
69/* Panel control registers */
70#define HOTPLUG_CTRL 0x61110
71#define PP_CONTROL 0x61204
Lee Leahy32471722015-04-20 15:20:28 -070072# define PP_CONTROL_WRITE_PROTECT_KEY 0xffff0000 /* Enable display port VDD */
73# define PP_CONTROL_UNLOCK 0xabcd0000
74# define PP_CONTROL_EDP_FORCE_VDD (1 << 3) /* Enable display port VDD */
75# define PP_CONTROL_BACKLIGHT_ENABLE (1 << 2)
76# define PP_CONTROL_POWER_DOWN_ON_RESET (1 << 1)
77# define PP_CONTROL_POWER_STATE_TARGET (1 << 0) /* Power up/down (1/0) */
78
Lee Leahy77ff0b12015-05-05 15:07:29 -070079#define PP_ON_DELAYS 0x61208
80#define PP_OFF_DELAYS 0x6120c
81#define PP_DIVISOR 0x61210
82#define BACKLIGHT_CTL2 0x61250
Lee Leahy32471722015-04-20 15:20:28 -070083# define BACKLIGHT_PWM_ENABLE (1 << 31)
84# define BACKLIGHT_POLARITY (1 << 28) /* Active low/high (1/0) */
85# define BACKLIGHT_PHASE_IN_INT_STATUS (1 << 26)
86# define BACKLIGHT_PHASE_IN_ENABLE (1 << 25)
87# define BACKLIGHT_PHASE_IN_INT_ENABLE (1 << 24)
88# define BACKLIGHT_PHASE_IN_TIME_BASE 0x00ff0000
89# define BACKLIGHT_PHASE_IN_COUNT 0x0000ff00
90# define BACKLIGHT_PHASE_IN_INCREMENT 0x000000ff
91
Lee Leahy77ff0b12015-05-05 15:07:29 -070092#define BACKLIGHT_CTL 0x61254
93
Lee Leahy32471722015-04-20 15:20:28 -070094#endif /* _SOC_GFX_H_ */