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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07006 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070016 */
17
18#include <arch/acpi.h>
19#include <arch/acpigen.h>
Lee Leahy32471722015-04-20 15:20:28 -070020#include <arch/cpu.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070021#include <arch/io.h>
22#include <arch/smp/mpspec.h>
Lee Leahy32471722015-04-20 15:20:28 -070023#include <cbfs.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070024#include <cbmem.h>
25#include <console/console.h>
Lee Leahy2bc9cee2015-06-30 15:25:44 -070026#include <cpu/cpu.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070027#include <cpu/intel/turbo.h>
Lee Leahy32471722015-04-20 15:20:28 -070028#include <cpu/x86/msr.h>
29#include <cpu/x86/smm.h>
30#include <cpu/x86/tsc.h>
31#include <device/pci.h>
32#include <device/pci_ids.h>
33#include <ec/google/chromeec/ec.h>
Patrick Rudolphc060fb52017-06-15 09:18:01 +020034#include <soc/intel/common/opregion.h>
Lee Leahyacb9c0b2015-07-02 11:55:18 -070035#include <rules.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070036#include <soc/acpi.h>
Lee Leahy32471722015-04-20 15:20:28 -070037#include <soc/gfx.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070038#include <soc/iomap.h>
39#include <soc/irq.h>
40#include <soc/msr.h>
41#include <soc/pattrs.h>
Lee Leahy32471722015-04-20 15:20:28 -070042#include <soc/pci_devs.h>
43#include <soc/pm.h>
44#include <string.h>
45#include <types.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070046#include <vendorcode/google/chromeos/gnvs.h>
Felix Durairaj15184e02015-11-23 14:07:40 -080047#include <wrdd.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070048
49#define MWAIT_RES(state, sub_state) \
50 { \
51 .addrl = (((state) << 4) | (sub_state)), \
52 .space_id = ACPI_ADDRESS_SPACE_FIXED, \
53 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
54 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
55 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
56 }
57
58/* C-state map without S0ix */
59static acpi_cstate_t cstate_map[] = {
60 {
61 /* C1 */
62 .ctype = 1, /* ACPI C1 */
63 .latency = 1,
64 .power = 1000,
65 .resource = MWAIT_RES(0, 0),
66 },
67 {
68 /* C6NS with no L2 shrink */
69 /* NOTE: this substate is above CPUID limit */
70 .ctype = 2, /* ACPI C2 */
71 .latency = 500,
72 .power = 10,
73 .resource = MWAIT_RES(5, 1),
74 },
75 {
76 /* C6FS with full L2 shrink */
77 .ctype = 3, /* ACPI C3 */
78 .latency = 1500, /* 1.5ms worst case */
79 .power = 1,
80 .resource = MWAIT_RES(5, 2),
81 }
82};
83
84void acpi_init_gnvs(global_nvs_t *gnvs)
85{
86 /* Set unknown wake source */
87 gnvs->pm1i = -1;
88
89 /* CPU core count */
90 gnvs->pcnt = dev_count_cpu();
91
92 /* Top of Low Memory (start of resource allocation) */
93 gnvs->tolm = nc_read_top_of_low_memory();
94
Lee Leahy32471722015-04-20 15:20:28 -070095#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
Lee Leahy77ff0b12015-05-05 15:07:29 -070096 /* Update the mem console pointer. */
97 gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
98#endif
99
Lee Leahy32471722015-04-20 15:20:28 -0700100#if IS_ENABLED(CONFIG_CHROMEOS)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700101 /* Initialize Verified Boot data */
102 chromeos_init_vboot(&(gnvs->chromeos));
Lee Leahy32471722015-04-20 15:20:28 -0700103#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700104 gnvs->chromeos.vbt2 = google_ec_running_ro() ?
105 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
106#endif
107#endif
108}
109
110static int acpi_sci_irq(void)
111{
112 u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
113 int scis;
114 static int sci_irq;
115
116 if (sci_irq)
117 return sci_irq;
118
119 /* Determine how SCI is routed. */
120 scis = read32(actl) & SCIS_MASK;
121 switch (scis) {
122 case SCIS_IRQ9:
123 case SCIS_IRQ10:
124 case SCIS_IRQ11:
125 sci_irq = scis - SCIS_IRQ9 + 9;
126 break;
127 case SCIS_IRQ20:
128 case SCIS_IRQ21:
129 case SCIS_IRQ22:
130 case SCIS_IRQ23:
131 sci_irq = scis - SCIS_IRQ20 + 20;
132 break;
133 default:
134 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
135 sci_irq = 9;
136 break;
137 }
138
139 printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
140 return sci_irq;
141}
142
Lee Leahy77ff0b12015-05-05 15:07:29 -0700143unsigned long acpi_fill_mcfg(unsigned long current)
144{
145 current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
146 MCFG_BASE_ADDRESS, 0, 0, 255);
147 return current;
148}
149
150void acpi_fill_in_fadt(acpi_fadt_t *fadt)
151{
152 const uint16_t pmbase = ACPI_BASE_ADDRESS;
153
154 fadt->sci_int = acpi_sci_irq();
155 fadt->smi_cmd = APM_CNT;
156 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
157 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
158 fadt->s4bios_req = 0x0;
159 fadt->pstate_cnt = 0;
160
161 fadt->pm1a_evt_blk = pmbase + PM1_STS;
162 fadt->pm1b_evt_blk = 0x0;
163 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
164 fadt->pm1b_cnt_blk = 0x0;
165 fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK;
166 fadt->pm_tmr_blk = pmbase + PM1_TMR;
167 fadt->gpe0_blk = pmbase + GPE0_STS;
168 fadt->gpe1_blk = 0;
169
170 fadt->pm1_evt_len = 4;
171 fadt->pm1_cnt_len = 2;
172 fadt->pm2_cnt_len = 1;
173 fadt->pm_tmr_len = 4;
174 fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
175 fadt->gpe1_blk_len = 0;
176 fadt->gpe1_base = 0;
177 fadt->cst_cnt = 0;
178 fadt->p_lvl2_lat = 1;
179 fadt->p_lvl3_lat = 87;
180 fadt->flush_size = 1024;
181 fadt->flush_stride = 16;
182 fadt->duty_offset = 1;
183 fadt->duty_width = 0;
184 fadt->day_alrm = 0xd;
185 fadt->mon_alrm = 0x00;
186 fadt->century = 0x00;
187 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
188
189 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
190 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
191 ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
192 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
193
194 fadt->reset_reg.space_id = 1;
195 fadt->reset_reg.bit_width = 8;
196 fadt->reset_reg.bit_offset = 0;
197 fadt->reset_reg.resv = 0;
198 fadt->reset_reg.addrl = 0xcf9;
199 fadt->reset_reg.addrh = 0;
200 fadt->reset_value = 6;
201
202 fadt->x_pm1a_evt_blk.space_id = 1;
203 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
204 fadt->x_pm1a_evt_blk.bit_offset = 0;
205 fadt->x_pm1a_evt_blk.resv = 0;
206 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
207 fadt->x_pm1a_evt_blk.addrh = 0x0;
208
209 fadt->x_pm1b_evt_blk.space_id = 1;
210 fadt->x_pm1b_evt_blk.bit_width = 0;
211 fadt->x_pm1b_evt_blk.bit_offset = 0;
212 fadt->x_pm1b_evt_blk.resv = 0;
213 fadt->x_pm1b_evt_blk.addrl = 0x0;
214 fadt->x_pm1b_evt_blk.addrh = 0x0;
215
216 fadt->x_pm1a_cnt_blk.space_id = 1;
217 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
218 fadt->x_pm1a_cnt_blk.bit_offset = 0;
219 fadt->x_pm1a_cnt_blk.resv = 0;
220 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
221 fadt->x_pm1a_cnt_blk.addrh = 0x0;
222
223 fadt->x_pm1b_cnt_blk.space_id = 1;
224 fadt->x_pm1b_cnt_blk.bit_width = 0;
225 fadt->x_pm1b_cnt_blk.bit_offset = 0;
226 fadt->x_pm1b_cnt_blk.resv = 0;
227 fadt->x_pm1b_cnt_blk.addrl = 0x0;
228 fadt->x_pm1b_cnt_blk.addrh = 0x0;
229
230 fadt->x_pm2_cnt_blk.space_id = 1;
231 fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
232 fadt->x_pm2_cnt_blk.bit_offset = 0;
233 fadt->x_pm2_cnt_blk.resv = 0;
234 fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK;
235 fadt->x_pm2_cnt_blk.addrh = 0x0;
236
237 fadt->x_pm_tmr_blk.space_id = 1;
238 fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
239 fadt->x_pm_tmr_blk.bit_offset = 0;
240 fadt->x_pm_tmr_blk.resv = 0;
241 fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
242 fadt->x_pm_tmr_blk.addrh = 0x0;
243
244 fadt->x_gpe0_blk.space_id = 1;
245 fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
246 fadt->x_gpe0_blk.bit_offset = 0;
247 fadt->x_gpe0_blk.resv = 0;
248 fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
249 fadt->x_gpe0_blk.addrh = 0x0;
250
251 fadt->x_gpe1_blk.space_id = 1;
252 fadt->x_gpe1_blk.bit_width = 0;
253 fadt->x_gpe1_blk.bit_offset = 0;
254 fadt->x_gpe1_blk.resv = 0;
255 fadt->x_gpe1_blk.addrl = 0x0;
256 fadt->x_gpe1_blk.addrh = 0x0;
257}
258
Lee Leahy32471722015-04-20 15:20:28 -0700259static acpi_tstate_t soc_tss_table[] = {
Lee Leahy77ff0b12015-05-05 15:07:29 -0700260 { 100, 1000, 0, 0x00, 0 },
261 { 88, 875, 0, 0x1e, 0 },
262 { 75, 750, 0, 0x1c, 0 },
263 { 63, 625, 0, 0x1a, 0 },
264 { 50, 500, 0, 0x18, 0 },
265 { 38, 375, 0, 0x16, 0 },
266 { 25, 250, 0, 0x14, 0 },
267 { 13, 125, 0, 0x12, 0 },
268};
269
Lee Leahyacb9c0b2015-07-02 11:55:18 -0700270static void generate_t_state_entries(int core, int cores_per_package)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700271{
Lee Leahy77ff0b12015-05-05 15:07:29 -0700272 /* Indicate SW_ALL coordination for T-states */
Lee Leahy32471722015-04-20 15:20:28 -0700273 acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700274
275 /* Indicate FFixedHW so OS will use MSR */
Lee Leahy32471722015-04-20 15:20:28 -0700276 acpigen_write_empty_PTC();
Lee Leahy77ff0b12015-05-05 15:07:29 -0700277
278 /* Set NVS controlled T-state limit */
Lee Leahy32471722015-04-20 15:20:28 -0700279 acpigen_write_TPC("\\TLVL");
Lee Leahy77ff0b12015-05-05 15:07:29 -0700280
281 /* Write TSS table for MSR access */
Lee Leahy32471722015-04-20 15:20:28 -0700282 acpigen_write_TSS_package(
283 ARRAY_SIZE(soc_tss_table), soc_tss_table);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700284}
285
286static int calculate_power(int tdp, int p1_ratio, int ratio)
287{
288 u32 m;
289 u32 power;
290
291 /*
292 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
293 *
294 * Power = (ratio / p1_ratio) * m * tdp
295 */
296
297 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
298 m = (m * m) / 1000;
299
300 power = ((ratio * 100000 / p1_ratio) / 100);
301 power *= (m / 100) * (tdp / 1000);
302 power /= 1000;
303
304 return (int)power;
305}
306
Lee Leahyacb9c0b2015-07-02 11:55:18 -0700307static void generate_p_state_entries(int core, int cores_per_package)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700308{
Lee Leahy77ff0b12015-05-05 15:07:29 -0700309 int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
310 int coord_type, power_max, power_unit, num_entries;
311 int ratio, power, clock, clock_max;
312 int vid, vid_turbo, vid_min, vid_max, vid_range_2;
313 u32 control_status;
314 const struct pattrs *pattrs = pattrs_get();
315 msr_t msr;
316
317 /* Inputs from CPU attributes */
318 ratio_max = pattrs->iacore_ratios[IACORE_MAX];
319 ratio_min = pattrs->iacore_ratios[IACORE_LFM];
320 vid_max = pattrs->iacore_vids[IACORE_MAX];
321 vid_min = pattrs->iacore_vids[IACORE_LFM];
322
323 /* Set P-states coordination type based on MSR disable bit */
324 coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
325
326 /* Max Non-Turbo Frequency */
327 clock_max = (ratio_max * pattrs->bclk_khz) / 1000;
328
329 /* Calculate CPU TDP in mW */
330 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
331 power_unit = 1 << (msr.lo & 0xf);
332 msr = rdmsr(MSR_PKG_POWER_LIMIT);
333 power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
334
335 /* Write _PCT indicating use of FFixedHW */
Lee Leahy32471722015-04-20 15:20:28 -0700336 acpigen_write_empty_PCT();
Lee Leahy77ff0b12015-05-05 15:07:29 -0700337
338 /* Write _PPC with NVS specified limit on supported P-state */
Lee Leahy32471722015-04-20 15:20:28 -0700339 acpigen_write_PPC_NVS();
Lee Leahy77ff0b12015-05-05 15:07:29 -0700340
341 /* Write PSD indicating configured coordination type */
Lee Leahy32471722015-04-20 15:20:28 -0700342 acpigen_write_PSD_package(core, 1, coord_type);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700343
344 /* Add P-state entries in _PSS table */
Lee Leahy32471722015-04-20 15:20:28 -0700345 acpigen_write_name("_PSS");
Lee Leahy77ff0b12015-05-05 15:07:29 -0700346
347 /* Determine ratio points */
348 ratio_step = 1;
349 num_entries = (ratio_max - ratio_min) / ratio_step;
350 while (num_entries > 15) { /* ACPI max is 15 ratios */
351 ratio_step <<= 1;
352 num_entries >>= 1;
353 }
354
355 /* P[T] is Turbo state if enabled */
356 if (get_turbo_state() == TURBO_ENABLED) {
357 /* _PSS package count including Turbo */
Lee Leahy32471722015-04-20 15:20:28 -0700358 acpigen_write_package(num_entries + 2);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700359
360 ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
361 vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
362 control_status = (ratio_turbo << 8) | vid_turbo;
363
364 /* Add entry for Turbo ratio */
Lee Leahy32471722015-04-20 15:20:28 -0700365 acpigen_write_PSS_package(
366 clock_max + 1, /* MHz */
367 power_max, /* mW */
368 10, /* lat1 */
369 10, /* lat2 */
370 control_status, /* control */
371 control_status); /* status */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700372 } else {
373 /* _PSS package count without Turbo */
Lee Leahy32471722015-04-20 15:20:28 -0700374 acpigen_write_package(num_entries + 1);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700375 ratio_turbo = ratio_max;
376 vid_turbo = vid_max;
377 }
378
379 /* First regular entry is max non-turbo ratio */
380 control_status = (ratio_max << 8) | vid_max;
Lee Leahy32471722015-04-20 15:20:28 -0700381 acpigen_write_PSS_package(
382 clock_max, /* MHz */
383 power_max, /* mW */
384 10, /* lat1 */
385 10, /* lat2 */
386 control_status, /* control */
387 control_status); /* status */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700388
389 /* Set up ratio and vid ranges for VID calculation */
390 ratio_range_2 = (ratio_turbo - ratio_min) * 2;
391 vid_range_2 = (vid_turbo - vid_min) * 2;
392
393 /* Generate the remaining entries */
394 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
395 ratio >= ratio_min; ratio -= ratio_step) {
396
397 /* Calculate VID for this ratio */
398 vid = ((ratio - ratio_min) * vid_range_2) /
399 ratio_range_2 + vid_min;
400 /* Round up if remainder */
401 if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
402 vid++;
403
404 /* Calculate power at this ratio */
405 power = calculate_power(power_max, ratio_max, ratio);
406 clock = (ratio * pattrs->bclk_khz) / 1000;
407 control_status = (ratio << 8) | (vid & 0xff);
408
Lee Leahy32471722015-04-20 15:20:28 -0700409 acpigen_write_PSS_package(
410 clock, /* MHz */
411 power, /* mW */
412 10, /* lat1 */
413 10, /* lat2 */
414 control_status, /* control */
415 control_status); /* status */
Lee Leahy77ff0b12015-05-05 15:07:29 -0700416 }
417
418 /* Fix package length */
Lee Leahy32471722015-04-20 15:20:28 -0700419 acpigen_pop_len();
Lee Leahy77ff0b12015-05-05 15:07:29 -0700420}
421
Lee Leahy32471722015-04-20 15:20:28 -0700422void generate_cpu_entries(device_t device)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700423{
Lee Leahy32471722015-04-20 15:20:28 -0700424 int core;
Lee Leahy77ff0b12015-05-05 15:07:29 -0700425 int pcontrol_blk = get_pmbase(), plen = 6;
426 const struct pattrs *pattrs = pattrs_get();
427
Lee Leahy32471722015-04-20 15:20:28 -0700428 for (core = 0; core < pattrs->num_cpus; core++) {
Lee Leahy77ff0b12015-05-05 15:07:29 -0700429 if (core > 0) {
430 pcontrol_blk = 0;
431 plen = 0;
432 }
433
434 /* Generate processor \_PR.CPUx */
Lee Leahy32471722015-04-20 15:20:28 -0700435 acpigen_write_processor(
Lee Leahy77ff0b12015-05-05 15:07:29 -0700436 core, pcontrol_blk, plen);
437
438 /* Generate P-state tables */
Lee Leahyacb9c0b2015-07-02 11:55:18 -0700439 generate_p_state_entries(
Lee Leahy77ff0b12015-05-05 15:07:29 -0700440 core, pattrs->num_cpus);
441
442 /* Generate C-state tables */
Lee Leahy32471722015-04-20 15:20:28 -0700443 acpigen_write_CST_package(
Lee Leahy77ff0b12015-05-05 15:07:29 -0700444 cstate_map, ARRAY_SIZE(cstate_map));
445
446 /* Generate T-state tables */
Lee Leahyacb9c0b2015-07-02 11:55:18 -0700447 generate_t_state_entries(
Lee Leahy77ff0b12015-05-05 15:07:29 -0700448 core, pattrs->num_cpus);
449
Lee Leahy32471722015-04-20 15:20:28 -0700450 acpigen_pop_len();
Lee Leahy77ff0b12015-05-05 15:07:29 -0700451 }
452}
453
454unsigned long acpi_madt_irq_overrides(unsigned long current)
455{
456 int sci_irq = acpi_sci_irq();
457 acpi_madt_irqoverride_t *irqovr;
458 uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
459
460 /* INT_SRC_OVR */
461 irqovr = (void *)current;
462 current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
463
464 if (sci_irq >= 20)
465 sci_flags |= MP_IRQ_POLARITY_LOW;
466 else
467 sci_flags |= MP_IRQ_POLARITY_HIGH;
468
469 irqovr = (void *)current;
470 current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
Lee Leahy32471722015-04-20 15:20:28 -0700471 sci_flags);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700472
473 return current;
474}
Lee Leahy32471722015-04-20 15:20:28 -0700475
Patrick Rudolphc060fb52017-06-15 09:18:01 +0200476/* Initialize IGD OpRegion, called from ACPI code */
477static int update_igd_opregion(igd_opregion_t *opregion)
478{
479 u16 reg16;
480 struct device *igd;
481
482 /* TODO Initialize Mailbox 1 */
Patrick Georgi0f68b232018-01-25 18:23:15 +0100483 opregion->mailbox1.clid = 1;
Patrick Rudolphc060fb52017-06-15 09:18:01 +0200484
485 /* TODO Initialize Mailbox 3 */
486 opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
487 opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
488 opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
489 opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
490 opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
491 opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
492 opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
493 opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
494 opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
495 opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
496 opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
497 opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
498 opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
499 opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
500 opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
501
502 /*
503 * TODO This needs to happen in S3 resume, too.
504 * Maybe it should move to the finalize handler
505 */
506 igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC));
507
508 pci_write_config32(igd, ASLS, (u32)opregion);
509 reg16 = pci_read_config16(igd, SWSCI);
510 reg16 &= ~(1 << 0);
511 reg16 |= (1 << 15);
512 pci_write_config16(igd, SWSCI, reg16);
513
514 return 0;
515}
516
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700517unsigned long southcluster_write_acpi_tables(device_t device,
518 unsigned long current,
519 struct acpi_rsdp *rsdp)
520{
521 acpi_header_t *ssdt2;
522
523 current = acpi_write_hpet(device, current, rsdp);
Aaron Durbin07a1b282015-12-10 17:07:38 -0600524 current = acpi_align_current(current);
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700525
Patrick Rudolphc060fb52017-06-15 09:18:01 +0200526 if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) {
Nico Huber2e7f6cc2017-05-22 15:58:03 +0200527 igd_opregion_t *opregion;
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700528
Nico Huber2e7f6cc2017-05-22 15:58:03 +0200529 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
530 opregion = (igd_opregion_t *)current;
531 init_igd_opregion(opregion);
Patrick Rudolphc060fb52017-06-15 09:18:01 +0200532 update_igd_opregion(opregion);
Nico Huber2e7f6cc2017-05-22 15:58:03 +0200533 current += sizeof(igd_opregion_t);
534 current = acpi_align_current(current);
535 }
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700536
537 ssdt2 = (acpi_header_t *)current;
538 memset(ssdt2, 0, sizeof(acpi_header_t));
539 acpi_create_serialio_ssdt(ssdt2);
540 if (ssdt2->length) {
541 current += ssdt2->length;
542 acpi_add_table(rsdp, ssdt2);
Lee Leahy6598b912017-03-16 17:30:09 -0700543 printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2,
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700544 ssdt2->length);
Aaron Durbin07a1b282015-12-10 17:07:38 -0600545 current = acpi_align_current(current);
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700546 } else {
547 ssdt2 = NULL;
548 printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n");
549 }
550
551 printk(BIOS_DEBUG, "current = %lx\n", current);
552
553 return current;
554}
555
556void southcluster_inject_dsdt(device_t device)
557{
558 global_nvs_t *gnvs;
559
560 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
561 if (!gnvs) {
Lee Leahy6598b912017-03-16 17:30:09 -0700562 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700563 if (gnvs)
564 memset(gnvs, 0, sizeof(*gnvs));
565 }
566
567 if (gnvs) {
568 acpi_create_gnvs(gnvs);
Felix Durairaj15184e02015-11-23 14:07:40 -0800569 /* Fill in the Wifi Region id */
Lee Leahyd94cff62017-03-16 17:49:42 -0700570 if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN))
Felix Durairaj15184e02015-11-23 14:07:40 -0800571 gnvs->cid1 = wifi_regulatory_domain();
Lee Leahyd94cff62017-03-16 17:49:42 -0700572 else
Felix Durairaj15184e02015-11-23 14:07:40 -0800573 gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
Lee Leahy2bc9cee2015-06-30 15:25:44 -0700574 acpi_save_gnvs((unsigned long)gnvs);
575 /* And tell SMI about it */
576 smm_setup_structures(gnvs, NULL, NULL);
577
578 /* Add it to DSDT. */
579 acpigen_write_scope("\\");
580 acpigen_write_name_dword("NVSA", (u32) gnvs);
581 acpigen_pop_len();
582 }
583}
584
585__attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
586{
587}