Lijian Zhao | aa3d78d | 2017-08-08 11:32:35 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2015-2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <intelblocks/systemagent.h> |
| 21 | #include <soc/iomap.h> |
| 22 | #include <soc/systemagent.h> |
| 23 | |
| 24 | /* |
| 25 | * SoC implementation |
| 26 | * |
| 27 | * Add all known fixed memory ranges for Host Controller/Mmeory |
| 28 | * controller. |
| 29 | */ |
| 30 | void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| 31 | { |
| 32 | static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
| 33 | { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, |
| 34 | "PCIEXBAR" }, |
| 35 | { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| 36 | { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, |
| 37 | { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, |
| 38 | { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, |
| 39 | { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, |
| 40 | }; |
| 41 | |
| 42 | sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| 43 | ARRAY_SIZE(soc_fixed_resources)); |
| 44 | } |
| 45 | |
| 46 | /* |
| 47 | * SoC implementation |
| 48 | * |
| 49 | * Perform System Agent Initialization during Ramstage phase. |
| 50 | */ |
| 51 | void soc_systemagent_init(struct device *dev) |
| 52 | { |
| 53 | /* Enable Power Aware Interrupt Routing */ |
| 54 | enable_power_aware_intr(); |
| 55 | |
| 56 | /* Enable BIOS Reset CPL */ |
| 57 | enable_bios_reset_cpl(); |
| 58 | } |