Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <chip.h> |
| 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/ioapic.h> |
| 25 | #include <arch/acpi.h> |
| 26 | #include <cpu/cpu.h> |
| 27 | #include <intelblocks/pcr.h> |
| 28 | #include <intelblocks/pmclib.h> |
| 29 | #include <intelblocks/rtc.h> |
| 30 | #include <pc80/mc146818rtc.h> |
| 31 | #include <string.h> |
| 32 | #include <soc/gpio.h> |
| 33 | #include <soc/iomap.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/pm.h> |
| 36 | #include <cpu/x86/smm.h> |
| 37 | #include <soc/pcr_ids.h> |
| 38 | #include <soc/ramstage.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 39 | #include <security/vboot/vbnv.h> |
| 40 | #include <security/vboot/vbnv_layout.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 41 | |
| 42 | static void pch_pmc_add_mmio_resources(device_t dev) |
| 43 | { |
| 44 | struct resource *res; |
| 45 | |
| 46 | /* Memory-mmapped I/O registers. */ |
| 47 | res = new_resource(dev, PWRMBASE); |
| 48 | res->base = PCH_PWRM_BASE_ADDRESS; |
| 49 | res->size = PCH_PWRM_BASE_SIZE; |
| 50 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 51 | IORESOURCE_FIXED | IORESOURCE_RESERVE; |
| 52 | } |
| 53 | |
| 54 | static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index) |
| 55 | { |
| 56 | struct resource *res; |
| 57 | res = new_resource(dev, index); |
| 58 | res->base = base; |
| 59 | res->size = size; |
| 60 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 61 | } |
| 62 | |
| 63 | static void pch_pmc_add_io_resources(device_t dev) |
| 64 | { |
| 65 | /* PMBASE */ |
| 66 | pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
| 67 | } |
| 68 | |
| 69 | static void pch_pmc_read_resources(device_t dev) |
| 70 | { |
| 71 | /* Get the normal PCI resources of this device. */ |
| 72 | pci_dev_read_resources(dev); |
| 73 | |
| 74 | /* Add non-standard MMIO resources. */ |
| 75 | pch_pmc_add_mmio_resources(dev); |
| 76 | |
| 77 | /* Add IO resources. */ |
| 78 | pch_pmc_add_io_resources(dev); |
| 79 | } |
| 80 | |
| 81 | static void pch_set_acpi_mode(void) |
| 82 | { |
| 83 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { |
| 84 | printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); |
| 85 | outb(APM_CNT_ACPI_DISABLE, APM_CNT); |
| 86 | printk(BIOS_DEBUG, "done.\n"); |
| 87 | } |
| 88 | } |
| 89 | |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 90 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 91 | { |
| 92 | uint32_t reg; |
| 93 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 94 | |
| 95 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 96 | enable ? "En" : "Dis", sx + '0'); |
| 97 | reg = read32(pmcbase + offset); |
| 98 | if (enable) |
| 99 | reg |= mask; |
| 100 | else |
| 101 | reg &= ~mask; |
| 102 | write32(pmcbase + offset, reg); |
| 103 | } |
| 104 | |
| 105 | static void config_deep_s5(int on_ac, int on_dc) |
| 106 | { |
| 107 | /* Treat S4 the same as S5. */ |
| 108 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 109 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 110 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 111 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 112 | } |
| 113 | |
| 114 | static void config_deep_s3(int on_ac, int on_dc) |
| 115 | { |
| 116 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 117 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 118 | } |
| 119 | |
| 120 | static void config_deep_sx(uint32_t deepsx_config) |
| 121 | { |
| 122 | uint32_t reg; |
| 123 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 124 | |
| 125 | reg = read32(pmcbase + DSX_CFG); |
| 126 | reg &= ~DSX_CFG_MASK; |
| 127 | reg |= deepsx_config; |
| 128 | write32(pmcbase + DSX_CFG, reg); |
| 129 | } |
| 130 | |
| 131 | static void pmc_init(struct device *dev) |
| 132 | { |
| 133 | config_t *config = dev->chip_info; |
| 134 | |
| 135 | rtc_init(); |
| 136 | |
| 137 | /* Initialize power management */ |
| 138 | pmc_gpe_init(); |
| 139 | |
| 140 | pch_set_acpi_mode(); |
| 141 | |
| 142 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 143 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 144 | config_deep_sx(config->deep_sx_config); |
| 145 | } |
| 146 | |
| 147 | static struct device_operations device_ops = { |
| 148 | .read_resources = &pch_pmc_read_resources, |
| 149 | .set_resources = &pci_dev_set_resources, |
| 150 | .enable_resources = &pci_dev_enable_resources, |
| 151 | .init = &pmc_init, |
| 152 | .scan_bus = &scan_lpc_bus, |
| 153 | }; |
| 154 | |
| 155 | static const unsigned short pci_device_ids[] = { |
| 156 | PCI_DEVICE_ID_INTEL_CNL_PMC, |
| 157 | 0 |
| 158 | }; |
| 159 | |
| 160 | static const struct pci_driver pch_lpc __pci_driver = { |
| 161 | .ops = &device_ops, |
| 162 | .vendor = PCI_VENDOR_ID_INTEL, |
| 163 | .devices = pci_device_ids, |
| 164 | }; |