blob: 02ee6fa02f910ab1fe2bba6a8a7f3663cbcc6e41 [file] [log] [blame]
Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
Marc Jones257db582017-06-18 17:33:30 -06004 * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc.
5 * Copyright (C) 2014 Google Inc.
Marc Jones24484842017-05-04 21:17:45 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
18 * ACPI - create the Fixed ACPI Description Tables (FADT)
19 */
20
21#include <string.h>
22#include <console/console.h>
23#include <arch/acpi.h>
Marc Jones257db582017-06-18 17:33:30 -060024#include <arch/acpigen.h>
Marc Jones24484842017-05-04 21:17:45 -060025#include <arch/io.h>
Marc Jones5ebc8652017-06-19 23:34:04 -060026#include <arch/ioapic.h>
Marshall Dawsone9b862e2017-09-22 15:14:46 -060027#include <cpu/x86/smm.h>
Marc Jones257db582017-06-18 17:33:30 -060028#include <cbmem.h>
Marc Jones24484842017-05-04 21:17:45 -060029#include <device/device.h>
Marc Jones6bfcf662017-08-06 17:42:35 -060030#include <device/pci.h>
Marc Jones257db582017-06-18 17:33:30 -060031#include <soc/acpi.h>
Chris Ching6a35fab2017-10-19 11:45:30 -060032#include <soc/pci_devs.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060033#include <soc/southbridge.h>
Marc Jones257db582017-06-18 17:33:30 -060034#include <soc/nvs.h>
Marc Jones24484842017-05-04 21:17:45 -060035
Marc Jones5ebc8652017-06-19 23:34:04 -060036unsigned long acpi_fill_madt(unsigned long current)
37{
38 /* create all subtables for processors */
39 current = acpi_create_madt_lapics(current);
40
41 /* Write Kern IOAPIC, only one */
42 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
43 CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
44
45 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
46 CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
47
48 /* 0: mean bus 0--->ISA */
49 /* 0: PIC 0 */
50 /* 2: APIC 2 */
51 /* 5 mean: 0101 --> Edge-triggered, Active high */
52 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
53 current, 0, 0, 2, 0);
54 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
55 current, 0, 9, 9, 0xF);
56
57 /* create all subtables for processors */
58 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
59 0xff, 5, 1);
60 /* 1: LINT1 connect to NMI */
61
62 return current;
63}
64
Marc Jones24484842017-05-04 21:17:45 -060065/*
66 * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
67 * in the ACPI 3.0b specification.
68 */
Marshall Dawson4e101ad2017-06-15 12:17:38 -060069void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
Marc Jones24484842017-05-04 21:17:45 -060070{
71 acpi_header_t *header = &(fadt->header);
72
73 printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE);
74
75 /* Prepare the header */
76 memset((void *)fadt, 0, sizeof(acpi_fadt_t));
77 memcpy(header->signature, "FACP", 4);
78 header->length = sizeof(acpi_fadt_t);
79 header->revision = ACPI_FADT_REV_ACPI_3_0;
80 memcpy(header->oem_id, OEM_ID, 6);
81 memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
82 memcpy(header->asl_compiler_id, ASLC, 4);
83 header->asl_compiler_revision = 0;
84
85 fadt->firmware_ctrl = (u32) facs;
86 fadt->dsdt = (u32) dsdt;
87 fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
88 fadt->preferred_pm_profile = FADT_PM_PROFILE;
Marc Jonesdfeb1c42017-08-07 19:08:24 -060089 fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */
Marc Jones24484842017-05-04 21:17:45 -060090
91 if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
Marshall Dawsone9b862e2017-09-22 15:14:46 -060092 fadt->smi_cmd = APM_CNT;
93 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
94 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
Marc Jones24484842017-05-04 21:17:45 -060095 fadt->s4bios_req = 0; /* Not supported */
96 fadt->pstate_cnt = 0; /* Not supported */
97 fadt->cst_cnt = 0; /* Not supported */
98 outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */
99 } else {
100 fadt->smi_cmd = 0; /* disable system management mode */
101 fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */
102 fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
103 fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */
104 fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */
105 fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */
106 outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
107 }
108
109 fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
110 fadt->pm1b_evt_blk = 0x0000;
111 fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
112 fadt->pm1b_cnt_blk = 0x0000;
113 fadt->pm2_cnt_blk = 0x0000;
114 fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
115 fadt->gpe0_blk = ACPI_GPE0_BLK;
Marc Jonesdfeb1c42017-08-07 19:08:24 -0600116 fadt->gpe1_blk = 0x0000; /* No gpe1 block */
Marc Jones24484842017-05-04 21:17:45 -0600117
118 fadt->pm1_evt_len = 4; /* 32 bits */
119 fadt->pm1_cnt_len = 2; /* 16 bits */
120 fadt->pm2_cnt_len = 0;
121 fadt->pm_tmr_len = 4; /* 32 bits */
122 fadt->gpe0_blk_len = 8; /* 64 bits */
123 fadt->gpe1_blk_len = 0;
124 fadt->gpe1_base = 0;
125
126 fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
127 fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
128 fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
129 fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
130 fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
131 fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
132 fadt->day_alrm = 0; /* 0x7d these have to be */
133 fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
134 fadt->century = 0; /* 0x7f to make rtc alarm work */
135 fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
136 fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
137 fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
138 ACPI_FADT_C1_SUPPORTED |
139 ACPI_FADT_SLEEP_BUTTON |
140 ACPI_FADT_S4_RTC_WAKE |
141 ACPI_FADT_32BIT_TIMER |
142 ACPI_FADT_RESET_REGISTER |
143 ACPI_FADT_PCI_EXPRESS_WAKE |
144 ACPI_FADT_PLATFORM_CLOCK |
145 ACPI_FADT_S4_RTC_VALID |
146 ACPI_FADT_REMOTE_POWER_ON;
147
148 /* Format is from 5.2.3.1: Generic Address Structure */
149 /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
150 /* 8 bit write of value 0x06 to 0xCF9 in IO space */
151 fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
152 fadt->reset_reg.bit_width = 8;
153 fadt->reset_reg.bit_offset = 0;
154 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600155 fadt->reset_reg.addrl = SYS_RESET;
Marc Jones24484842017-05-04 21:17:45 -0600156 fadt->reset_reg.addrh = 0x0;
157
158 fadt->reset_value = 6;
159
160 fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */
161 fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */
162 fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */
163
164 fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
165 fadt->x_firmware_ctl_h = 0;
166 fadt->x_dsdt_l = (u32) dsdt;
167 fadt->x_dsdt_h = 0;
168
169 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
170 fadt->x_pm1a_evt_blk.bit_width = 32;
171 fadt->x_pm1a_evt_blk.bit_offset = 0;
172 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
173 fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
174 fadt->x_pm1a_evt_blk.addrh = 0x0;
175
176 fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
177 fadt->x_pm1b_evt_blk.bit_width = 0;
178 fadt->x_pm1b_evt_blk.bit_offset = 0;
179 fadt->x_pm1b_evt_blk.access_size = 0;
180 fadt->x_pm1b_evt_blk.addrl = 0x0;
181 fadt->x_pm1b_evt_blk.addrh = 0x0;
182
183
184 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
185 fadt->x_pm1a_cnt_blk.bit_width = 16;
186 fadt->x_pm1a_cnt_blk.bit_offset = 0;
187 fadt->x_pm1a_cnt_blk.access_size = 0;
188 fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
189 fadt->x_pm1a_cnt_blk.addrh = 0x0;
190
191 fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
192 fadt->x_pm1b_cnt_blk.bit_width = 0;
193 fadt->x_pm1b_cnt_blk.bit_offset = 0;
194 fadt->x_pm1b_cnt_blk.access_size = 0;
195 fadt->x_pm1b_cnt_blk.addrl = 0x0;
196 fadt->x_pm1b_cnt_blk.addrh = 0x0;
197
198 /*
Marshall Dawson4e101ad2017-06-15 12:17:38 -0600199 * Note: Under this current AMD C state implementation, this is no
200 * longer used and should not be reported to OS.
Marc Jones24484842017-05-04 21:17:45 -0600201 */
202 fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
203 fadt->x_pm2_cnt_blk.bit_width = 0;
204 fadt->x_pm2_cnt_blk.bit_offset = 0;
205 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
206 fadt->x_pm2_cnt_blk.addrl = 0;
207 fadt->x_pm2_cnt_blk.addrh = 0x0;
208
209
210 fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
211 fadt->x_pm_tmr_blk.bit_width = 32;
212 fadt->x_pm_tmr_blk.bit_offset = 0;
213 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
214 fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
215 fadt->x_pm_tmr_blk.addrh = 0x0;
216
217
218 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
219 fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
220 fadt->x_gpe0_blk.bit_offset = 0;
221 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
222 fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
223 fadt->x_gpe0_blk.addrh = 0x0;
224
225
226 fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
227 fadt->x_gpe1_blk.bit_width = 0;
228 fadt->x_gpe1_blk.bit_offset = 0;
229 fadt->x_gpe1_blk.access_size = 0;
230 fadt->x_gpe1_blk.addrl = 0;
231 fadt->x_gpe1_blk.addrh = 0x0;
232
233 header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
234}
Marc Jones257db582017-06-18 17:33:30 -0600235
Marc Jones6bfcf662017-08-06 17:42:35 -0600236void generate_cpu_entries(device_t device)
237{
238 int cores, cpu, plen = 6;
239 u32 pcontrol_blk = ACPI_GPE0_BLK;
240 device_t cdb_dev;
241
242 /* Stoney Ridge is single node, just report # of cores */
Chris Ching6a35fab2017-10-19 11:45:30 -0600243 cdb_dev = dev_find_slot(0, NB_DEVFN);
Marc Jones6bfcf662017-08-06 17:42:35 -0600244 cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
245
246 printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
247
Marc Jonese013df92017-08-23 16:28:02 -0600248 /* Generate BSP \_PR.P000 */
Marc Jones6bfcf662017-08-06 17:42:35 -0600249 acpigen_write_processor(0, pcontrol_blk, plen);
250 acpigen_pop_len();
251
Marc Jonese013df92017-08-23 16:28:02 -0600252 /* Generate AP \_PR.Pxxx */
Marc Jones6bfcf662017-08-06 17:42:35 -0600253 pcontrol_blk = 0;
254 plen = 0;
255 for (cpu = 1; cpu < cores; cpu++) {
256 acpigen_write_processor(cpu, pcontrol_blk, 0);
257 acpigen_pop_len();
258 }
259}
260
Marc Jones257db582017-06-18 17:33:30 -0600261unsigned long southbridge_write_acpi_tables(device_t device,
262 unsigned long current,
263 struct acpi_rsdp *rsdp)
264{
265 return acpi_write_hpet(device, current, rsdp);
266}
267
268static void acpi_create_gnvs(struct global_nvs_t *gnvs)
269{
270 /* Clear out GNVS. */
271 memset(gnvs, 0, sizeof(*gnvs));
272
273 if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
274 gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
275
276 if (IS_ENABLED(CONFIG_CHROMEOS)) {
277 /* Initialize Verified Boot data */
278 chromeos_init_vboot(&gnvs->chromeos);
279 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
280 }
281
282 /* Set unknown wake source */
283 gnvs->pm1i = ~0ULL;
284
285 /* CPU core count */
286 gnvs->pcnt = dev_count_cpu();
287}
288
289void southbridge_inject_dsdt(device_t device)
290{
291 struct global_nvs_t *gnvs;
292
293 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
294
295 if (gnvs) {
296 acpi_create_gnvs(gnvs);
297 acpi_save_gnvs((uintptr_t)gnvs);
298
299 /* Add it to DSDT */
300 acpigen_write_scope("\\");
301 acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
302 acpigen_pop_len();
303 }
304}