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Marc Jones24484842017-05-04 21:17:45 -06001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2017 Advanced Micro Devices, Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
Marc Jones21cde8b2017-05-07 16:47:36 -060016config SOC_AMD_STONEYRIDGE_FP4
Marc Jones24484842017-05-04 21:17:45 -060017 bool
Marc Jones21cde8b2017-05-07 16:47:36 -060018 help
19 AMD Stoney Ridge FP4 support
20
21config SOC_AMD_STONEYRIDGE_FT4
22 bool
23 help
24 AMD Stoney Ridge FT4 support
25
26if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
27
28config CPU_SPECIFIC_OPTIONS
29 def_bool y
30 select ARCH_BOOTBLOCK_X86_32
31 select ARCH_VERSTAGE_X86_32
32 select ARCH_ROMSTAGE_X86_32
33 select ARCH_RAMSTAGE_X86_32
Marshall Dawson68592c32017-11-06 10:56:52 -070034 select ACPI_AMD_HARDWARE_SLEEP_VALUES
Marc Jones9156cac2017-07-12 11:05:38 -060035 select GENERIC_GPIO_LIB
Marc Jones24484842017-05-04 21:17:45 -060036 select IOAPIC
37 select HAVE_USBDEBUG_OPTIONS
38 select HAVE_HARD_RESET
Marshall Dawson786bd5d2017-06-16 10:10:17 -060039 select UDELAY_TSC
40 select HAVE_MONOTONIC_TIMER
41 select TSC_MONOTONIC_TIMER
42 select TSC_CONSTANT_RATE
Marc Jones21cde8b2017-05-07 16:47:36 -060043 select SPI_FLASH if HAVE_ACPI_RESUME
44 select TSC_SYNC_LFENCE
Marshall Dawson9df969a2017-07-25 18:46:46 -060045 select COLLECT_TIMESTAMPS
Marc Jones1587dc82017-05-15 18:55:11 -060046 select SOC_AMD_PI
Marshall Dawson68243a52017-06-15 16:59:20 -060047 select SOC_AMD_COMMON
48 select SOC_AMD_COMMON_BLOCK
Richard Spiegel2bbc3dc2017-12-06 16:14:58 -070049 select SOC_AMD_COMMON_BLOCK_PCI
Marshall Dawson68243a52017-06-15 16:59:20 -060050 select SOC_AMD_COMMON_BLOCK_PSP
Marshall Dawson9df969a2017-07-25 18:46:46 -060051 select SOC_AMD_COMMON_BLOCK_CAR
Richard Spiegel2bbc3dc2017-12-06 16:14:58 -070052 select SOC_AMD_COMMON_BLOCK_S3
Marshall Dawson9df969a2017-07-25 18:46:46 -060053 select C_ENVIRONMENT_BOOTBLOCK
54 select BOOTBLOCK_CONSOLE
John E. Kabat Jraf327702017-11-29 18:49:37 -070055 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
Marshall Dawsona7bfbbe2017-09-13 17:24:53 -060056 select RELOCATABLE_MODULES
57 select PARALLEL_MP
Marc Jones33eef132017-10-26 16:50:42 -060058 select PARALLEL_MP_AP_WORK
Marshall Dawsonb6172112017-09-13 17:47:31 -060059 select HAVE_SMI_HANDLER
60 select SMM_TSEG
Marshall Dawson18b477e2017-09-21 12:27:12 -060061 select RELOCATABLE_RAMSTAGE
62 select POSTCAR_STAGE
63 select POSTCAR_CONSOLE
Martin Roth37b8bde2017-09-26 09:41:10 -060064 select SSE
65 select SSE2
Marc Jones24484842017-05-04 21:17:45 -060066
Marshall Dawsone7557de2017-06-09 16:35:14 -060067config VBOOT
Marshall Dawsone7557de2017-06-09 16:35:14 -060068 select VBOOT_SEPARATE_VERSTAGE
69 select VBOOT_STARTS_IN_BOOTBLOCK
70 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
71
Marc Jones21cde8b2017-05-07 16:47:36 -060072config UDELAY_LAPIC_FIXED_FSB
73 int
74 default 200
75
76# TODO: Sync these with definitions in PI vendorcode.
77# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
78# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
79
80config DCACHE_RAM_BASE
81 hex
82 default 0x30000
83
84config DCACHE_RAM_SIZE
85 hex
86 default 0x10000
87
Marshall Dawson9df969a2017-07-25 18:46:46 -060088config DCACHE_BSP_STACK_SIZE
89 depends on C_ENVIRONMENT_BOOTBLOCK
90 hex
91 default 0x4000
92 help
93 The amount of anticipated stack usage in CAR by bootblock and
94 other stages.
95
Marshall Dawson7c3f1e72017-08-24 09:59:10 -060096config PRERAM_CBMEM_CONSOLE_SIZE
97 hex
98 default 0x1200
99 help
100 Increase this value if preram cbmem console is getting truncated
101
Marc Jones21cde8b2017-05-07 16:47:36 -0600102config CPU_ADDR_BITS
103 int
104 default 48
105
Marc Jones1587dc82017-05-15 18:55:11 -0600106config BOTTOMIO_POSITION
107 hex "Bottom of 32-bit IO space"
108 default 0xD0000000
109 help
110 If PCI peripherals with big BARs are connected to the system
111 the bottom of the IO must be decreased to allocate such
112 devices.
113
114 Declare the beginning of the 128MB-aligned MMIO region. This
115 option is useful when PCI peripherals requesting large address
116 ranges are present.
117
Marc Jones1587dc82017-05-15 18:55:11 -0600118config MMCONF_BASE_ADDRESS
119 hex
120 default 0xF8000000
121
122config MMCONF_BUS_NUMBER
123 int
124 default 64
125
126config VGA_BIOS_ID
127 string
128 default "1002,98e4"
129 help
130 The default VGA BIOS PCI vendor/device ID should be set to the
131 result of the map_oprom_vendev() function in northbridge.c.
132
133config VGA_BIOS_FILE
134 string
135 default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin"
136
137config RAMTOP
138 hex
139 default 0x1000000
140
141config HEAP_SIZE
142 hex
143 default 0xc0000
144
145config RAMBASE
146 hex
147 default 0x200000
148
Marc Jones24484842017-05-04 21:17:45 -0600149config SOUTHBRIDGE_AMD_STONEYRIDGE_SKIP_ISA_DMA_INIT
150 bool
151 default n
152
153config EHCI_BAR
154 hex
155 default 0xfef00000
156
157config STONEYRIDGE_XHCI_ENABLE
158 bool "Enable Stoney Ridge XHCI Controller"
159 default y
160 help
161 The XHCI controller must be enabled and the XHCI firmware
162 must be added in order to have USB 3.0 support configured
163 by coreboot. The OS will be responsible for enabling the XHCI
164 controller if the the XHCI firmware is available but the
165 XHCI controller is not enabled by coreboot.
166
167config STONEYRIDGE_XHCI_FWM
168 bool "Add xhci firmware"
169 default y
170 help
171 Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
172
173config STONEYRIDGE_IMC_FWM
174 bool "Add IMC firmware"
175 default n
176 help
177 Add Stoney Ridge IMC Firmware to support the onboard fan control
178
179config STONEYRIDGE_GEC_FWM
180 bool
181 default n
182 help
183 Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
184 Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
185
186config STONEYRIDGE_XHCI_FWM_FILE
187 string "XHCI firmware path and filename"
188 default "3rdparty/blobs/southbridge/amd/kern/xhci.bin"
189 depends on STONEYRIDGE_XHCI_FWM
190
191config STONEYRIDGE_IMC_FWM_FILE
192 string "IMC firmware path and filename"
193 default "3rdparty/blobs/southbridge/amd/kern/imc.bin"
194 depends on STONEYRIDGE_IMC_FWM
195
196config STONEYRIDGE_GEC_FWM_FILE
197 string "GEC firmware path and filename"
198 depends on STONEYRIDGE_GEC_FWM
199
200config AMD_PUBKEY_FILE
201 string "AMD public Key"
202 default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyST.bin"
203
204config STONEYRIDGE_SATA_MODE
205 int "SATA Mode"
206 default 0
207 range 0 6
208 help
209 Select the mode in which SATA should be driven.
210 The default is NATIVE.
211 0: NATIVE mode does not require a ROM.
212 2: AHCI may work with or without AHCI ROM. It depends on the payload support.
213 For example, seabios does not require the AHCI ROM.
214 3: LEGACY IDE
215 4: IDE to AHCI
216 5: AHCI7804: ROM Required, and AMD driver required in the OS.
217 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
218
219comment "NATIVE"
220 depends on STONEYRIDGE_SATA_MODE = 0
221
222comment "AHCI"
223 depends on STONEYRIDGE_SATA_MODE = 2
224
225comment "LEGACY IDE"
226 depends on STONEYRIDGE_SATA_MODE = 3
227
228comment "IDE to AHCI"
229 depends on STONEYRIDGE_SATA_MODE = 4
230
231comment "AHCI7804"
232 depends on STONEYRIDGE_SATA_MODE = 5
233
234comment "IDE to AHCI7804"
235 depends on STONEYRIDGE_SATA_MODE = 6
236
237if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
238
239config AHCI_ROM_ID
240 string "AHCI device PCI IDs"
241 default "1022,7801" if STONEYRIDGE_SATA_MODE = 2
242 default "1022,7804" if STONEYRIDGE_SATA_MODE = 5
243
244endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
245
246config STONEYRIDGE_LEGACY_FREE
247 bool "System is legacy free"
248 help
249 Select y if there is no keyboard controller in the system.
250 This sets variables in AGESA and ACPI.
251
Marc Jones24484842017-05-04 21:17:45 -0600252config SERIRQ_CONTINUOUS_MODE
253 bool
254 default n
255 help
256 Set this option to y for serial IRQ in continuous mode.
257 Otherwise it is in quiet mode.
258
259config STONEYRIDGE_ACPI_IO_BASE
260 hex
261 default 0x400
262 help
263 Base address for the ACPI registers.
264 This value must match the hardcoded value of AGESA.
265
266config STONEYRIDGE_UART
267 bool "UART controller on Stoney Ridge"
268 default n
269 select DRIVERS_UART_8250MEM
270 select DRIVERS_UART_8250MEM_32
271 select NO_UART_ON_SUPERIO
272 select UART_OVERRIDE_REFCLK
273 help
274 There are two UART controllers in Stoney Ridge.
275 The UART registers are memory-mapped. UART
276 controller 0 registers range from FEDC_6000h
277 to FEDC_6FFFh. UART controller 1 registers
278 range from FEDC_8000h to FEDC_8FFFh.
279
Marshall Dawsonc6ef9db2017-05-14 14:16:56 -0600280config SMM_TSEG_SIZE
281 hex
Marshall Dawson0801b332017-08-25 15:29:45 -0600282 default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
Marshall Dawsonc6ef9db2017-05-14 14:16:56 -0600283 default 0x0
284
Marshall Dawsonb6172112017-09-13 17:47:31 -0600285config SMM_RESERVED_SIZE
286 hex
287 default 0x100000
288
Marc Jonese013df92017-08-23 16:28:02 -0600289config ACPI_CPU_STRING
290 string
291 default "\\_PR.P%03d"
292
Martin Rothb617e322017-09-07 13:23:55 -0600293config USE_PSPSCUREOS
294 bool "Include PSP SecureOS blobs in AMD firmware"
295 default y
296 help
297 Include the PspSecureOs, PspTrustlet and TrustletKey binaries
298 in the amdfw section.
299
300 If unsure, answer 'y'
301
Marshall Dawson5f0520a2017-10-30 16:11:45 -0600302config SOC_AMD_SMU_FANLESS
303 bool
304 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
305 default n if SOC_AMD_SMU_NOTFANLESS
306 default y
307
308config SOC_AMD_SMU_FANNED
309 bool
310 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
311 default n
312 select SOC_AMD_SMU_NOTFANLESS
313
314config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use
315 bool
316 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW
317
Martin Roth30f9b952017-10-03 15:54:45 -0600318config AMDFW_OUTSIDE_CBFS
319 bool "The AMD firmware is outside CBFS"
320 default n
321 help
322 The AMDFW (PSP) is typically locatable in cbfs. Select this
323 option to manually attach the generated amdfw.rom outside of
324 cbfs. The location is selected by the FWM position.
325
Martin Roth6d8ef242017-09-08 14:39:35 -0600326config AMD_FWM_POSITION_INDEX
327 int "Firmware Directory Table location (0 to 5)"
328 range 0 5
329 default 0 if BOARD_ROMSIZE_KB_512
330 default 1 if BOARD_ROMSIZE_KB_1024
331 default 2 if BOARD_ROMSIZE_KB_2048
332 default 3 if BOARD_ROMSIZE_KB_4096
333 default 4 if BOARD_ROMSIZE_KB_8192
334 default 5 if BOARD_ROMSIZE_KB_16384
335 help
336 Typically this is calculated by the ROM size, but there may
337 be situations where you want to put the firmware directory
338 table in a different location.
339 0: 512 KB - 0xFFFA0000
340 1: 1 MB - 0xFFF20000
341 2: 2 MB - 0xFFE20000
342 3: 4 MB - 0xFFC20000
343 4: 8 MB - 0xFF820000
344 5: 16 MB - 0xFF020000
345
346comment "AMD Firmware Directory Table set to location for 512KB ROM"
347 depends on AMD_FWM_POSITION_INDEX = 0
348comment "AMD Firmware Directory Table set to location for 1MB ROM"
349 depends on AMD_FWM_POSITION_INDEX = 1
350comment "AMD Firmware Directory Table set to location for 2MB ROM"
351 depends on AMD_FWM_POSITION_INDEX = 2
352comment "AMD Firmware Directory Table set to location for 4MB ROM"
353 depends on AMD_FWM_POSITION_INDEX = 3
354comment "AMD Firmware Directory Table set to location for 8MB ROM"
355 depends on AMD_FWM_POSITION_INDEX = 4
356comment "AMD Firmware Directory Table set to location for 16MB ROM"
357 depends on AMD_FWM_POSITION_INDEX = 5
358
Marc Jones17431ab2017-11-16 15:26:00 -0700359config DIMM_SPD_SIZE
360 int
361 default 512 # DDR4
362
Marc Jones578a79d2017-12-06 16:27:04 -0700363config RO_REGION_ONLY
364 string
365 depends on CHROMEOS
366 default "apu/amdfw"
367
Marc Jones21cde8b2017-05-07 16:47:36 -0600368endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4