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Alexandru Gagniuc88a30232013-06-04 23:37:56 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050015 */
16
17#include "early_vx900.h"
18#include <arch/io.h>
19#include <console/console.h>
20
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050021/**
22 * \brief Enable accessing of PCI configuration space for all devices.
23 *
24 * Enable accessing of D0F1 through D0F7, which would otherwise not be
25 * accessible. If MMCONF is enabled, configure it here. This is the first
26 * function that should be called in romstage.
27 */
28void vx900_enable_pci_config_space(void)
29{
30 /* MMCONF is not yet enabled, so we'll need to specify we want to do
31 * pci_io. We don't want to do pci_mmio until we enable it */
32 /* Enable multifunction bit for northbridge.
33 * This enables the PCI configuration spaces of D0F1 to D0F7 to be
34 * accessed */
35 pci_io_write_config8(HOST_CTR, 0x4f, 0x01);
36
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050037 /* COOL, now enable MMCONF */
38 u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60);
39 reg8 |= 3;
40 pci_io_write_config8(TRAF_CTR, 0x60, reg8);
Kyösti Mälkki6f66f412016-12-01 22:08:18 +020041
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050042 reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28;
43 pci_io_write_config8(TRAF_CTR, 0x61, reg8);
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050044}
45
46/**
47 *\brief Prints information regarding the hardware strapping on VX900
48 *
49 * Certain features on the VX900 are controlled by strapping pins which are
50 * hardwired on the mainboard. These values determine whether the ROM is on the
51 * SPI or LPC bus, or whether auto-reset is enabled.
52 * \n
53 * Having a feel for these values is important when trying to fix obscure
54 * problems found when porting a mainboard based on the VX900.
55 * \n
56 * These values are decoded and printed to the terminal.
57 */
58void vx900_print_strapping_info(void)
59{
60 u8 strap = pci_read_config8(SNMIC, 0x56);
61
Stefan Reinauer65b72ab2015-01-05 12:59:54 -080062 printk(BIOS_DEBUG, "VX900 strapping pins indicate that:\n");
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050063 printk(BIOS_DEBUG, " ROM is on %s bus\n",
64 (strap & (1 << 0)) ? "SPI" : "LPC");
65 printk(BIOS_DEBUG, " Auto reset is %s\n",
66 (strap & (1 << 1)) ? "disabled" : "enabled");
67 printk(BIOS_DEBUG, " LPC FWH command is %s\n",
68 (strap & (1 << 2)) ? "enabled" : "disabled");
69 printk(BIOS_DEBUG, " Debug link is is %s\n",
70 (strap & (1 << 4)) ? "enabled" : "disabled");
71 printk(BIOS_DEBUG, " PCI master mode is %s\n",
72 (strap & (1 << 5)) ? "enabled" : "disabled");
73}
74
75/**
76 *\brief Disables the auto-reboot mechanism on VX900
77 *
78 * The VX900 has an auto-reboot mechanism that can be enabled by a hardware
79 * strap. This mechanism can make development annoying, since we don't know if
80 * the reset was caused by a bug in coreboot, or by this mechanism.
81 */
82void vx900_disable_auto_reboot(void)
83{
84 if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) {
Stefan Reinauer65b72ab2015-01-05 12:59:54 -080085 printk(BIOS_DEBUG, "Auto-reboot is disabled in hardware\n");
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050086 return;
87 }
88 /* Disable the GP3 timer, which is the root of all evil */
89 pci_write_config8(LPC, 0x98, 0);
90 /* Yep, that's all it takes */
Stefan Reinauer65b72ab2015-01-05 12:59:54 -080091 printk(BIOS_DEBUG, "GP3 timer disabled."
Alexandru Gagniuc88a30232013-06-04 23:37:56 -050092 " Auto-reboot should not give you any more trouble.\n");
93}
94
95/**
96 * \brief Disables 'shadowing' of system ROM
97 *
98 * Disable unnecessary shadowing of the ROM in the first 1MB of address space.
Martin Rothe18e6422017-06-03 20:03:18 -060099 * coreboot runs in 32-bit mode from the start. Shadowing only gets in the way.
Alexandru Gagniuc88a30232013-06-04 23:37:56 -0500100 * This function frees the entire 640k-1M range for DRAM. VGA may still use
101 * the 640k-768k range, if enabled later.
102 */
103void vx900_disable_legacy_rom_shadow(void)
104{
105 pci_write_config8(MCU, 0x80, 0xff); /* LPC ROM 768k - 832k */
106 pci_write_config8(MCU, 0x81, 0xff); /* LPC ROM 832k - 896k */
107 pci_write_config8(MCU, 0x82, 0xff); /* LPC ROM 896k - 960k */
108 /* LPC ROM 960k - 1M * SMRAM: 640k - 768k */
109 pci_write_config8(MCU, 0x83, 0x31);
110
111 /* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */
112 pci_mod_config8(LPC, 0x41, 1 << 7, 0); /* LPC ROM 896k - 960k */
113
114 pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */
115 pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */
116 pci_write_config8(SNMIC, 0x63, 0); /* 896k - 1M */
117 pci_write_config8(SNMIC, 0x64, 0); /* 896k - 960k */
118}
119
120/**
121 * \brief Disables the VX900 integrated graphics controller
122 *
123 * Disable the graphics controller entirely. It will no longer be visible as a
124 * PCI device.
125 */
126void vx900_disable_gfx(void)
127{
128 /* Disable GFX */
129 pci_mod_config8(MCU, 0xa1, 1 << 7, 0);
130}