blob: 11123b6e11b9c5824f1cd925b59c0676676bce4a [file] [log] [blame]
Lubomir Rintel71053a92017-10-31 10:02:27 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <arch/io.h>
18
19#if CONFIG_ROM_SIZE == 0x80000
20# define ROM_DECODE_MAP 0x00
21#elif CONFIG_ROM_SIZE == 0x100000
22# define ROM_DECODE_MAP 0x40
23#elif CONFIG_ROM_SIZE == 0x180000
24# define ROM_DECODE_MAP 0x60
25#elif CONFIG_ROM_SIZE == 0x200000
26# define ROM_DECODE_MAP 0x70
27#elif CONFIG_ROM_SIZE == 0x280000
28# define ROM_DECODE_MAP 0x78
29#elif CONFIG_ROM_SIZE == 0x300000
30# define ROM_DECODE_MAP 0x7c
31#elif CONFIG_ROM_SIZE == 0x380000
32# define ROM_DECODE_MAP 0x7e
33#elif CONFIG_ROM_SIZE == 0x400000
34# define ROM_DECODE_MAP 0x7f
35#else
36# error "Bad CONFIG_ROM_SIZE"
37#endif
38
39static void bootblock_northbridge_init(void)
40{
41 u8 reg;
42
43 pci_io_read_config8(PCI_DEV(0, 0x11, 0), 0x41);
44 reg |= ROM_DECODE_MAP;
45 pci_io_write_config8(PCI_DEV(0, 0x11, 0), 0x41, reg);
46}