Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor PCH Datasheet |
| 5 | * Document number: 621483 |
| 6 | * Chapter number: 4, 29 |
| 7 | */ |
| 8 | |
| 9 | #include <arch/io.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 10 | #include <bootstate.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 11 | #include <commonlib/console/post_codes.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 12 | #include <console/console.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 13 | #include <cpu/x86/smm.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 14 | #include <device/mmio.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | #include <device/pci.h> |
| 16 | #include <intelblocks/lpc_lib.h> |
| 17 | #include <intelblocks/pcr.h> |
| 18 | #include <intelblocks/pmclib.h> |
| 19 | #include <intelblocks/tco.h> |
| 20 | #include <intelblocks/thermal.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <soc/p2sb.h> |
| 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/pcr_ids.h> |
| 24 | #include <soc/pm.h> |
| 25 | #include <soc/smbus.h> |
| 26 | #include <soc/soc_chip.h> |
| 27 | #include <soc/systemagent.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 28 | #include <spi-generic.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 29 | |
| 30 | #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ |
| 31 | #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ |
| 32 | #define CAM_CLK_EN (1 << 1) |
| 33 | #define MIPI_CLK (1 << 0) |
| 34 | #define HDPLL_CLK (0 << 0) |
| 35 | |
| 36 | static void pch_enable_isclk(void) |
| 37 | { |
| 38 | pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); |
| 39 | pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); |
| 40 | } |
| 41 | |
| 42 | static void pch_handle_sideband(config_t *config) |
| 43 | { |
| 44 | if (config->pch_isclk) |
| 45 | pch_enable_isclk(); |
| 46 | } |
| 47 | |
| 48 | static void pch_finalize(void) |
| 49 | { |
| 50 | config_t *config; |
| 51 | |
| 52 | /* TCO Lock down */ |
| 53 | tco_lockdown(); |
| 54 | |
| 55 | /* TODO: Add Thermal Configuration */ |
| 56 | |
| 57 | /* |
| 58 | * Disable ACPI PM timer based on dt policy |
| 59 | * |
| 60 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 61 | * Disabling ACPI PM timer also switches off TCO |
| 62 | */ |
| 63 | config = config_of_soc(); |
| 64 | if (config->PmTimerDisabled) |
| 65 | pmc_disable_acpi_timer(); |
| 66 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 67 | pch_handle_sideband(config); |
| 68 | |
| 69 | pmc_clear_pmcon_sts(); |
| 70 | } |
| 71 | |
| 72 | static void tbt_finalize(void) |
| 73 | { |
| 74 | int i; |
| 75 | const struct device *dev; |
| 76 | |
| 77 | /* Disable Thunderbolt PCIe root ports bus master */ |
| 78 | for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { |
| 79 | dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); |
| 80 | if (dev) |
| 81 | pci_dev_disable_bus_master(dev); |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | static void soc_finalize(void *unused) |
| 86 | { |
| 87 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 88 | |
| 89 | pch_finalize(); |
| 90 | apm_control(APM_CNT_FINALIZE); |
| 91 | tbt_finalize(); |
| 92 | |
| 93 | /* Indicate finalize step with post code */ |
| 94 | post_code(POST_OS_BOOT); |
| 95 | } |
| 96 | |
| 97 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 98 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |