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Subrata Banik2871e0e2020-09-27 11:30:58 +05301/* SPDX-License-Identifier: GPL-2.0-only */
2
3/*
4 * This file is created based on Intel Alder Lake Processor PCH Datasheet
5 * Document number: 621483
6 * Chapter number: 4, 29
7 */
8
9#include <arch/io.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053010#include <bootstate.h>
Ricardo Quesada470ca5712021-07-16 16:39:28 -070011#include <commonlib/console/post_codes.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053012#include <console/console.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053013#include <cpu/x86/smm.h>
Ricardo Quesada470ca5712021-07-16 16:39:28 -070014#include <device/mmio.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053015#include <device/pci.h>
16#include <intelblocks/lpc_lib.h>
17#include <intelblocks/pcr.h>
18#include <intelblocks/pmclib.h>
19#include <intelblocks/tco.h>
20#include <intelblocks/thermal.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053021#include <soc/p2sb.h>
22#include <soc/pci_devs.h>
23#include <soc/pcr_ids.h>
24#include <soc/pm.h>
25#include <soc/smbus.h>
26#include <soc/soc_chip.h>
27#include <soc/systemagent.h>
Ricardo Quesada470ca5712021-07-16 16:39:28 -070028#include <spi-generic.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053029
30#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
31#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
32#define CAM_CLK_EN (1 << 1)
33#define MIPI_CLK (1 << 0)
34#define HDPLL_CLK (0 << 0)
35
36static void pch_enable_isclk(void)
37{
38 pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
39 pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
40}
41
42static void pch_handle_sideband(config_t *config)
43{
44 if (config->pch_isclk)
45 pch_enable_isclk();
46}
47
48static void pch_finalize(void)
49{
50 config_t *config;
51
52 /* TCO Lock down */
53 tco_lockdown();
54
55 /* TODO: Add Thermal Configuration */
56
57 /*
58 * Disable ACPI PM timer based on dt policy
59 *
60 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
61 * Disabling ACPI PM timer also switches off TCO
62 */
63 config = config_of_soc();
64 if (config->PmTimerDisabled)
65 pmc_disable_acpi_timer();
66
Subrata Banik2871e0e2020-09-27 11:30:58 +053067 pch_handle_sideband(config);
68
69 pmc_clear_pmcon_sts();
70}
71
72static void tbt_finalize(void)
73{
74 int i;
75 const struct device *dev;
76
77 /* Disable Thunderbolt PCIe root ports bus master */
78 for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
79 dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
80 if (dev)
81 pci_dev_disable_bus_master(dev);
82 }
83}
84
85static void soc_finalize(void *unused)
86{
87 printk(BIOS_DEBUG, "Finalizing chipset.\n");
88
89 pch_finalize();
90 apm_control(APM_CNT_FINALIZE);
91 tbt_finalize();
92
93 /* Indicate finalize step with post code */
94 post_code(POST_OS_BOOT);
95}
96
97BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
98BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);