Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 3 | #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ |
| 4 | #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 5 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 6 | #define DEFAULT_HECIBAR ((u8 *)0xfed17000) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 7 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 8 | |
| 9 | #define IOMMU_BASE1 0xfed90000 |
| 10 | #define IOMMU_BASE2 0xfed91000 |
| 11 | #define IOMMU_BASE3 0xfed92000 |
| 12 | #define IOMMU_BASE4 0xfed93000 |
| 13 | |
| 14 | /* |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 15 | * D1:F0 PEG |
| 16 | */ |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 17 | #define PEG_CAP 0xa2 |
| 18 | #define SLOTCAP 0xb4 |
| 19 | #define PEGLC 0xec |
| 20 | #define D1F0_VCCAP 0x104 |
| 21 | #define D1F0_VC0RCTL 0x114 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 22 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 23 | /* Chipset types */ |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 24 | #define IRONLAKE_MOBILE 0 |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 25 | #define IRONLAKE_DESKTOP 1 |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 26 | #define IRONLAKE_SERVER 2 |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 27 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 28 | /* Northbridge BARs */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 29 | #ifndef __ACPI__ |
| 30 | #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ |
| 31 | #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ |
| 32 | #else |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 33 | #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ |
| 34 | #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 35 | #endif |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 36 | #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 37 | #define DEFAULT_RCBABASE ((u8 *)0xfed1c000) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 38 | |
| 39 | #define QUICKPATH_BUS 0xff |
| 40 | |
| 41 | #include <southbridge/intel/ibexpeak/pch.h> |
| 42 | |
| 43 | /* Everything below this line is ignored in the DSDT */ |
| 44 | #ifndef __ACPI__ |
| 45 | |
| 46 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
| 47 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 48 | #include "hostbridge_regs.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 49 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 50 | /* |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 51 | * SAD - System Address Decoder |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 52 | */ |
Angel Pons | 3ab19b3 | 2020-07-22 16:29:54 +0200 | [diff] [blame] | 53 | #define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) |
| 54 | |
Angel Pons | e9d1d70 | 2020-07-22 12:47:00 +0200 | [diff] [blame] | 55 | #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ |
Vladimir Serbinenko | 786c0f5 | 2014-01-02 10:16:46 +0100 | [diff] [blame] | 56 | #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 57 | |
Angel Pons | 4500893 | 2020-07-22 16:43:48 +0200 | [diff] [blame] | 58 | #define SAD_PCIEXBAR 0x50 |
| 59 | |
Angel Pons | 6757337 | 2020-07-22 16:56:00 +0200 | [diff] [blame] | 60 | #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ |
| 61 | #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ |
| 62 | |
Angel Pons | 93d9517 | 2020-07-22 17:30:49 +0200 | [diff] [blame^] | 63 | /* |
| 64 | * QPI Link 0 |
| 65 | */ |
| 66 | #define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) |
| 67 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 68 | |
| 69 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 70 | |
| 71 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * MCHBAR |
| 75 | */ |
| 76 | |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 77 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 78 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 79 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) |
| 80 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 81 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 82 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 83 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 84 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 85 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 86 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 87 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 88 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 89 | /* |
| 90 | * EPBAR - Egress Port Root Complex Register Block |
| 91 | */ |
| 92 | |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 93 | #define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) |
| 94 | #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) |
| 95 | #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 96 | |
| 97 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 98 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 99 | |
| 100 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 101 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 102 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 103 | |
| 104 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 105 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 106 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 107 | |
| 108 | #define EPVC1MTS 0x028 /* 32bit */ |
| 109 | #define EPVC1IST 0x038 /* 64bit */ |
| 110 | |
| 111 | #define EPESD 0x044 /* 32bit */ |
| 112 | |
| 113 | #define EPLE1D 0x050 /* 32bit */ |
| 114 | #define EPLE1A 0x058 /* 64bit */ |
| 115 | #define EPLE2D 0x060 /* 32bit */ |
| 116 | #define EPLE2A 0x068 /* 64bit */ |
| 117 | |
| 118 | #define PORTARB 0x100 /* 256bit */ |
| 119 | |
| 120 | /* |
| 121 | * DMIBAR |
| 122 | */ |
| 123 | |
Angel Pons | dd6a3d8 | 2020-06-22 17:21:23 +0200 | [diff] [blame] | 124 | #define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) |
| 125 | #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) |
| 126 | #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 127 | |
| 128 | #define DMIVCECH 0x000 /* 32bit */ |
| 129 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 130 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 131 | |
| 132 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 133 | |
| 134 | #define DMIVC0RCAP 0x010 /* 32bit */ |
Felix Held | 00d2b91 | 2018-07-28 21:06:01 +0200 | [diff] [blame] | 135 | #define DMIVC0RCTL 0x014 /* 32bit */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 136 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 137 | |
| 138 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 139 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 140 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 141 | |
| 142 | #define DMILE1D 0x050 /* 32bit */ |
| 143 | #define DMILE1A 0x058 /* 64bit */ |
| 144 | #define DMILE2D 0x060 /* 32bit */ |
| 145 | #define DMILE2A 0x068 /* 64bit */ |
| 146 | |
| 147 | #define DMILCAP 0x084 /* 32bit */ |
| 148 | #define DMILCTL 0x088 /* 16bit */ |
| 149 | #define DMILSTS 0x08a /* 16bit */ |
| 150 | |
| 151 | #define DMICTL1 0x0f0 /* 32bit */ |
| 152 | #define DMICTL2 0x0fc /* 32bit */ |
| 153 | |
| 154 | #define DMICC 0x208 /* 32bit */ |
| 155 | |
| 156 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 157 | |
| 158 | #ifndef __ASSEMBLER__ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 159 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 160 | void intel_ironlake_finalize_smm(void); |
Kyösti Mälkki | 82c0e7e | 2019-11-05 19:06:56 +0200 | [diff] [blame] | 161 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 162 | int bridge_silicon_revision(void); |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 163 | void ironlake_early_initialization(int chipset_type); |
| 164 | void ironlake_late_initialization(void); |
Arthur Heymans | cea4fd9 | 2019-10-03 08:54:35 +0200 | [diff] [blame] | 165 | void mainboard_pre_raminit(void); |
| 166 | void mainboard_get_spd_map(u8 *spd_addrmap); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 167 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 168 | #endif |
| 169 | #endif |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 170 | #endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ |