Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Arastra, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
| 17 | #include <stdlib.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/pnp_def.h> |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 22 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 23 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 24 | #include <console/console.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 25 | #include "southbridge/intel/i3100/early_smbus.c" |
| 26 | #include "southbridge/intel/i3100/early_lpc.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 27 | #include <northbridge/intel/i3100/raminit.h> |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 28 | #include <superio/intel/i3100/i3100.h> |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 29 | #include "northbridge/intel/i3100/memory_initialized.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <cpu/x86/bist.h> |
Kyösti Mälkki | 07921540d | 2016-06-17 17:22:00 +0300 | [diff] [blame^] | 31 | #include <cpu/intel/romstage.h> |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 32 | #include <spd.h> |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 33 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 34 | #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) |
| 35 | #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) |
| 36 | |
Uwe Hermann | d1a1d57 | 2010-11-10 18:22:11 +0000 | [diff] [blame] | 37 | #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) |
| 38 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 39 | static inline int spd_read_byte(u16 device, u8 address) |
| 40 | { |
| 41 | return smbus_read_byte(device, address); |
| 42 | } |
| 43 | |
| 44 | #include "northbridge/intel/i3100/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 45 | #include "lib/generic_sdram.c" |
Myles Watson | 8377c2d | 2010-09-02 22:02:53 +0000 | [diff] [blame] | 46 | #if 0 /* skip_romstage doesn't compile with gcc */ |
Stefan Reinauer | 8677a23 | 2010-12-11 20:33:41 +0000 | [diff] [blame] | 47 | #include "arch/x86/lib/stages.c" |
Myles Watson | 8377c2d | 2010-09-02 22:02:53 +0000 | [diff] [blame] | 48 | #endif |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 49 | |
Kyösti Mälkki | 07921540d | 2016-06-17 17:22:00 +0300 | [diff] [blame^] | 50 | void mainboard_romstage_entry(unsigned long bist) |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 51 | { |
| 52 | msr_t msr; |
| 53 | u16 perf; |
| 54 | static const struct mem_controller mch[] = { |
| 55 | { |
| 56 | .node_id = 0, |
| 57 | .f0 = PCI_DEV(0, 0x00, 0), |
| 58 | .f1 = PCI_DEV(0, 0x00, 1), |
| 59 | .f2 = PCI_DEV(0, 0x00, 2), |
| 60 | .f3 = PCI_DEV(0, 0x00, 3), |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 61 | .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 }, |
| 62 | .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 }, |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 63 | } |
| 64 | }; |
| 65 | |
| 66 | if (bist == 0) { |
Myles Watson | 8377c2d | 2010-09-02 22:02:53 +0000 | [diff] [blame] | 67 | #if 0 /* skip_romstage doesn't compile with gcc */ |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 68 | /* Skip this if there was a built in self test failure */ |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 69 | if (memory_initialized()) { |
Stefan Reinauer | d41a0bc | 2010-04-09 13:33:59 +0000 | [diff] [blame] | 70 | skip_romstage(); |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 71 | } |
Myles Watson | 8377c2d | 2010-09-02 22:02:53 +0000 | [diff] [blame] | 72 | #endif |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 73 | } |
Uwe Hermann | d1a1d57 | 2010-11-10 18:22:11 +0000 | [diff] [blame] | 74 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 75 | /* Set up the console */ |
| 76 | i3100_enable_superio(); |
Uwe Hermann | d1a1d57 | 2010-11-10 18:22:11 +0000 | [diff] [blame] | 77 | i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 78 | i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); |
| 79 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 80 | console_init(); |
| 81 | |
Ed Swierk | 71f846c | 2008-03-30 11:31:15 +0000 | [diff] [blame] | 82 | /* Prevent the TCO timer from rebooting us */ |
| 83 | i3100_halt_tco_timer(); |
| 84 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 85 | /* Halt if there was a built in self test failure */ |
| 86 | report_bist_failure(bist); |
| 87 | |
| 88 | /* print_pci_devices(); */ |
| 89 | enable_smbus(); |
| 90 | /* dump_spd_registers(); */ |
| 91 | |
| 92 | /* Enable SpeedStep and automatic thermal throttling */ |
| 93 | /* FIXME: move to Pentium M init code */ |
| 94 | msr = rdmsr(0x1a0); |
| 95 | msr.lo |= (1 << 3) | (1 << 16); |
| 96 | wrmsr(0x1a0, msr); |
| 97 | msr = rdmsr(0x19d); |
| 98 | msr.lo |= (1 << 16); |
| 99 | wrmsr(0x19d, msr); |
| 100 | |
| 101 | /* Set CPU frequency/voltage to maximum */ |
| 102 | /* FIXME: move to Pentium M init code */ |
| 103 | msr = rdmsr(0x198); |
| 104 | perf = msr.hi & 0xffff; |
| 105 | msr = rdmsr(0x199); |
| 106 | msr.lo &= 0xffff0000; |
| 107 | msr.lo |= perf; |
| 108 | wrmsr(0x199, msr); |
| 109 | |
| 110 | sdram_initialize(ARRAY_SIZE(mch), mch); |
| 111 | /* dump_pci_devices(); */ |
| 112 | /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */ |
| 113 | /* dump_bar14(PCI_DEV(0, 0x00, 0)); */ |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 114 | } |