Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/acpi.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <stdint.h> |
| 21 | #include <delay.h> |
| 22 | #include <cpu/intel/haswell/haswell.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | #include <stdlib.h> |
| 27 | #include <string.h> |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 28 | #include <cpu/x86/smm.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | #include <boot/tables.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | #include "chip.h" |
| 31 | #include "haswell.h" |
| 32 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 33 | static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, |
| 34 | u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | u32 pciexbar_reg; |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 37 | u32 mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | |
| 39 | *base = 0; |
| 40 | *len = 0; |
| 41 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 42 | pciexbar_reg = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | |
| 44 | if (!(pciexbar_reg & (1 << 0))) |
| 45 | return 0; |
| 46 | |
| 47 | switch ((pciexbar_reg >> 1) & 3) { |
| 48 | case 0: // 256MB |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 49 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 50 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | *len = 256 * 1024 * 1024; |
| 52 | return 1; |
| 53 | case 1: // 128M |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 54 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 55 | mask |= (1 << 27); |
| 56 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | *len = 128 * 1024 * 1024; |
| 58 | return 1; |
| 59 | case 2: // 64M |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 60 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 61 | mask |= (1 << 27) | (1 << 26); |
| 62 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 63 | *len = 64 * 1024 * 1024; |
| 64 | return 1; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 70 | static void pci_domain_set_resources(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 72 | assign_resources(dev->link_list); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | } |
| 74 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 75 | static const char *northbridge_acpi_name(const struct device *dev) |
| 76 | { |
| 77 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 78 | return "PCI0"; |
| 79 | |
| 80 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 81 | return NULL; |
| 82 | |
| 83 | switch (dev->path.pci.devfn) { |
| 84 | case PCI_DEVFN(0, 0): |
| 85 | return "MCHC"; |
| 86 | } |
| 87 | |
| 88 | return NULL; |
| 89 | } |
| 90 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | /* TODO We could determine how many PCIe busses we need in |
| 92 | * the bar. For now that number is hardcoded to a max of 64. |
| 93 | * See e7525/northbridge.c for an example. |
| 94 | */ |
| 95 | static struct device_operations pci_domain_ops = { |
| 96 | .read_resources = pci_domain_read_resources, |
| 97 | .set_resources = pci_domain_set_resources, |
| 98 | .enable_resources = NULL, |
| 99 | .init = NULL, |
| 100 | .scan_bus = pci_domain_scan_bus, |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 101 | .acpi_name = northbridge_acpi_name, |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 102 | .write_acpi_tables = northbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | }; |
| 104 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 105 | static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 107 | u32 bar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 109 | bar = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 111 | /* If not enabled don't report it. */ |
| 112 | if (!(bar & 0x1)) |
| 113 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 114 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 115 | /* Knock down the enable bit. */ |
| 116 | *base = bar & ~1; |
| 117 | |
| 118 | return 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 119 | } |
| 120 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 121 | /* There are special BARs that actually are programmed in the MCHBAR. These |
| 122 | * Intel special features, but they do consume resources that need to be |
| 123 | * accounted for. */ |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 124 | static int get_bar_in_mchbar(struct device *dev, unsigned int index, |
| 125 | u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 127 | u32 bar; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 129 | bar = MCHBAR32(index); |
| 130 | |
| 131 | /* If not enabled don't report it. */ |
| 132 | if (!(bar & 0x1)) |
| 133 | return 0; |
| 134 | |
| 135 | /* Knock down the enable bit. */ |
| 136 | *base = bar & ~1; |
| 137 | |
| 138 | return 1; |
| 139 | } |
| 140 | |
| 141 | struct fixed_mmio_descriptor { |
| 142 | unsigned int index; |
| 143 | u32 size; |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 144 | int (*get_resource)(struct device *dev, unsigned int index, |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 145 | u32 *base, u32 *size); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 146 | const char *description; |
| 147 | }; |
| 148 | |
| 149 | #define SIZE_KB(x) ((x)*1024) |
| 150 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 151 | { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, |
| 152 | { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, |
| 153 | { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, |
| 154 | { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, |
| 155 | { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, |
| 156 | { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, |
| 157 | }; |
| 158 | #undef SIZE_KB |
| 159 | |
| 160 | /* |
| 161 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 162 | * controller device. |
| 163 | */ |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 164 | static void mc_add_fixed_mmio_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 165 | { |
| 166 | int i; |
| 167 | |
| 168 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 169 | u32 base; |
| 170 | u32 size; |
| 171 | struct resource *resource; |
| 172 | unsigned int index; |
| 173 | |
| 174 | size = mc_fixed_resources[i].size; |
| 175 | index = mc_fixed_resources[i].index; |
| 176 | if (!mc_fixed_resources[i].get_resource(dev, index, |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 177 | &base, &size)) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 178 | continue; |
| 179 | |
| 180 | resource = new_resource(dev, mc_fixed_resources[i].index); |
| 181 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 182 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 183 | IORESOURCE_ASSIGNED; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 184 | resource->base = base; |
| 185 | resource->size = size; |
| 186 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 187 | __func__, mc_fixed_resources[i].description, index, |
| 188 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | /* Host Memory Map: |
| 193 | * |
| 194 | * +--------------------------+ TOUUD |
| 195 | * | | |
| 196 | * +--------------------------+ 4GiB |
| 197 | * | PCI Address Space | |
| 198 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 199 | * | iGD | |
| 200 | * +--------------------------+ BDSM |
| 201 | * | GTT | |
| 202 | * +--------------------------+ BGSM |
| 203 | * | TSEG | |
| 204 | * +--------------------------+ TSEGMB |
| 205 | * | Usage DRAM | |
| 206 | * +--------------------------+ 0 |
| 207 | * |
| 208 | * Some of the base registers above can be equal making the size of those |
| 209 | * regions 0. The reason is because the memory controller internally subtracts |
| 210 | * the base registers from each other to determine sizes of the regions. In |
| 211 | * other words, the memory map is in a fixed order no matter what. |
| 212 | */ |
| 213 | |
| 214 | struct map_entry { |
| 215 | int reg; |
| 216 | int is_64_bit; |
| 217 | int is_limit; |
| 218 | const char *description; |
| 219 | }; |
| 220 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 221 | static void read_map_entry(struct device *dev, struct map_entry *entry, |
| 222 | uint64_t *result) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 223 | { |
| 224 | uint64_t value; |
| 225 | uint64_t mask; |
| 226 | |
| 227 | /* All registers are on a 1MiB granularity. */ |
| 228 | mask = ((1ULL<<20)-1); |
| 229 | mask = ~mask; |
| 230 | |
| 231 | value = 0; |
| 232 | |
| 233 | if (entry->is_64_bit) { |
| 234 | value = pci_read_config32(dev, entry->reg + 4); |
| 235 | value <<= 32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 236 | } |
| 237 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 238 | value |= pci_read_config32(dev, entry->reg); |
| 239 | value &= mask; |
| 240 | |
| 241 | if (entry->is_limit) |
| 242 | value |= ~mask; |
| 243 | |
| 244 | *result = value; |
| 245 | } |
| 246 | |
| 247 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 248 | { \ |
| 249 | .reg = reg_, \ |
| 250 | .is_64_bit = is_64_, \ |
| 251 | .is_limit = is_limit_, \ |
| 252 | .description = desc_, \ |
| 253 | } |
| 254 | |
| 255 | #define MAP_ENTRY_BASE_64(reg_, desc_) \ |
| 256 | MAP_ENTRY(reg_, 1, 0, desc_) |
| 257 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) \ |
| 258 | MAP_ENTRY(reg_, 1, 1, desc_) |
| 259 | #define MAP_ENTRY_BASE_32(reg_, desc_) \ |
| 260 | MAP_ENTRY(reg_, 0, 0, desc_) |
| 261 | |
| 262 | enum { |
| 263 | TOM_REG, |
| 264 | TOUUD_REG, |
| 265 | MESEG_BASE_REG, |
| 266 | MESEG_LIMIT_REG, |
| 267 | REMAP_BASE_REG, |
| 268 | REMAP_LIMIT_REG, |
| 269 | TOLUD_REG, |
| 270 | BGSM_REG, |
| 271 | BDSM_REG, |
| 272 | TSEG_REG, |
| 273 | // Must be last. |
| 274 | NUM_MAP_ENTRIES |
| 275 | }; |
| 276 | |
| 277 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 278 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 279 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 280 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
| 281 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
| 282 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
| 283 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
| 284 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
Aaron Durbin | 1570260 | 2012-12-21 22:18:58 -0600 | [diff] [blame] | 285 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 286 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 287 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), |
| 288 | }; |
| 289 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 290 | static void mc_read_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 291 | { |
| 292 | int i; |
| 293 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 294 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 295 | } |
| 296 | } |
| 297 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 298 | static void mc_report_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 299 | { |
| 300 | int i; |
| 301 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 302 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 303 | memory_map[i].description, values[i]); |
| 304 | } |
| 305 | /* One can validate the BDSM and BGSM against the GGC. */ |
| 306 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 307 | } |
| 308 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 309 | static void mc_add_dram_resources(struct device *dev, int *resource_cnt) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 310 | { |
| 311 | unsigned long base_k, size_k; |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 312 | unsigned long touud_k; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 313 | unsigned long index; |
| 314 | struct resource *resource; |
| 315 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 316 | |
| 317 | /* Read in the MAP registers and report their values. */ |
| 318 | mc_read_map_entries(dev, &mc_values[0]); |
| 319 | mc_report_map_entries(dev, &mc_values[0]); |
| 320 | |
| 321 | /* |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 322 | * These are the host memory ranges that should be added: |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 323 | * - 0 -> 0xa0000: cacheable |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 324 | * - 0xc0000 -> TSEG : cacheable |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 325 | * - TESG -> BGSM: cacheable with standard MTRRs and reserved |
| 326 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 327 | * - 4GiB -> TOUUD: cacheable |
| 328 | * |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 329 | * The default SMRAM space is reserved so that the range doesn't |
| 330 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 331 | * cannot use the memory. This is a bit of an odd place to reserve |
| 332 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 333 | * called on them. |
| 334 | * |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 335 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 336 | * associated with it to handle legacy VGA memory. If this range |
| 337 | * is not omitted the mtrr code will setup the area as cacheable |
| 338 | * causing VGA access to not work. |
| 339 | * |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 340 | * The TSEG region is mapped as cacheable so that one can perform |
| 341 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 342 | * precedence over the existing MTRRs covering this region. |
| 343 | * |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 344 | * It should be noted that cacheable entry types need to be added in |
| 345 | * order. The reason is that the current MTRR code assumes this and |
| 346 | * falls over itself if it isn't. |
| 347 | * |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 348 | * The resource index starts low and should not meet or exceed |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 349 | * PCI_BASE_ADDRESS_0. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 350 | */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 351 | index = *resource_cnt; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 352 | |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 353 | /* 0 - > 0xa0000 */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 354 | base_k = 0; |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 355 | size_k = (0xa0000 >> 10) - base_k; |
| 356 | ram_resource(dev, index++, base_k, size_k); |
| 357 | |
| 358 | /* 0xc0000 -> TSEG */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 359 | base_k = 0xc0000 >> 10; |
| 360 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; |
| 361 | ram_resource(dev, index++, base_k, size_k); |
| 362 | |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 363 | /* TSEG -> BGSM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 364 | resource = new_resource(dev, index++); |
| 365 | resource->base = mc_values[TSEG_REG]; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 366 | resource->size = mc_values[BGSM_REG] - resource->base; |
| 367 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 368 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 369 | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 370 | |
| 371 | /* BGSM -> TOLUD */ |
| 372 | resource = new_resource(dev, index++); |
| 373 | resource->base = mc_values[BGSM_REG]; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 374 | resource->size = mc_values[TOLUD_REG] - resource->base; |
| 375 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 376 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 377 | IORESOURCE_ASSIGNED; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 378 | |
| 379 | /* 4GiB -> TOUUD */ |
| 380 | base_k = 4096 * 1024; /* 4GiB */ |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 381 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 382 | size_k = touud_k - base_k; |
| 383 | if (touud_k > base_k) |
Aaron Durbin | 5c66f08 | 2013-01-08 10:10:33 -0600 | [diff] [blame] | 384 | ram_resource(dev, index++, base_k, size_k); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 385 | |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 386 | /* Reserve everything between A segment and 1MB: |
| 387 | * |
| 388 | * 0xa0000 - 0xbffff: legacy VGA |
| 389 | * 0xc0000 - 0xfffff: RAM |
| 390 | */ |
| 391 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
| 392 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 393 | (0x100000 - 0xc0000) >> 10); |
Martin Roth | 3323260 | 2017-06-24 14:48:50 -0600 | [diff] [blame] | 394 | #if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 395 | reserved_ram_resource(dev, index++, |
| 396 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 397 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 398 | #endif |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 399 | *resource_cnt = index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 400 | } |
| 401 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 402 | static void mc_read_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 403 | { |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 404 | int index = 0; |
| 405 | const bool vtd_capable = |
| 406 | !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); |
| 407 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 408 | /* Read standard PCI resources. */ |
| 409 | pci_dev_read_resources(dev); |
| 410 | |
| 411 | /* Add all fixed MMIO resources. */ |
| 412 | mc_add_fixed_mmio_resources(dev); |
| 413 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 414 | /* Add VT-d MMIO resources if capable */ |
| 415 | if (vtd_capable) { |
| 416 | mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, |
| 417 | GFXVT_BASE_SIZE / KiB); |
| 418 | mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, |
| 419 | VTVC0_BASE_SIZE / KiB); |
| 420 | } |
| 421 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 422 | /* Calculate and add DRAM resources. */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 423 | mc_add_dram_resources(dev, &index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 424 | } |
| 425 | |
Elyes HAOUAS | b60920d | 2018-09-20 17:38:38 +0200 | [diff] [blame] | 426 | static void intel_set_subsystem(struct device *dev, unsigned int vendor, |
| 427 | unsigned int device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 428 | { |
| 429 | if (!vendor || !device) { |
| 430 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 431 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 432 | } else { |
| 433 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 434 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 435 | } |
| 436 | } |
| 437 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 438 | static void northbridge_init(struct device *dev) |
| 439 | { |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 440 | u8 bios_reset_cpl, pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 441 | |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 442 | /* Enable Power Aware Interrupt Routing */ |
| 443 | pair = MCHBAR8(0x5418); |
| 444 | pair &= ~0x7; /* Clear 2:0 */ |
| 445 | pair |= 0x4; /* Fixed Priority */ |
| 446 | MCHBAR8(0x5418) = pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 447 | |
| 448 | /* |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 449 | * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 450 | * that BIOS has initialized memory and power management |
| 451 | */ |
| 452 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 453 | bios_reset_cpl |= 3; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 454 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 455 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 456 | |
| 457 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 458 | mdelay(1); |
| 459 | set_power_limits(28); |
| 460 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 461 | /* Set here before graphics PM init */ |
| 462 | MCHBAR32(0x5500) = 0x00100001; |
| 463 | } |
| 464 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 465 | static struct pci_operations intel_pci_ops = { |
| 466 | .set_subsystem = intel_set_subsystem, |
| 467 | }; |
| 468 | |
| 469 | static struct device_operations mc_ops = { |
| 470 | .read_resources = mc_read_resources, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 471 | .set_resources = pci_dev_set_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 472 | .enable_resources = pci_dev_enable_resources, |
| 473 | .init = northbridge_init, |
Vladimir Serbinenko | 0a66991 | 2014-10-05 14:34:17 +0200 | [diff] [blame] | 474 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 475 | .scan_bus = 0, |
| 476 | .ops_pci = &intel_pci_ops, |
| 477 | }; |
| 478 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 479 | static const unsigned short mc_pci_device_ids[] = { |
| 480 | 0x0c00, /* Desktop */ |
| 481 | 0x0c04, /* Mobile */ |
| 482 | 0x0a04, /* ULT */ |
| 483 | 0 |
Tristan Corrick | 4817012 | 2018-10-31 02:21:41 +1300 | [diff] [blame] | 484 | }; |
| 485 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 486 | static const struct pci_driver mc_driver_hsw __pci_driver = { |
| 487 | .ops = &mc_ops, |
| 488 | .vendor = PCI_VENDOR_ID_INTEL, |
| 489 | .devices = mc_pci_device_ids, |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 490 | }; |
| 491 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 492 | static void cpu_bus_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 493 | { |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 494 | bsp_init_and_start_aps(dev->link_list); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 495 | } |
| 496 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 497 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 498 | .read_resources = DEVICE_NOOP, |
| 499 | .set_resources = DEVICE_NOOP, |
| 500 | .enable_resources = DEVICE_NOOP, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 501 | .init = cpu_bus_init, |
| 502 | .scan_bus = 0, |
| 503 | }; |
| 504 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 505 | static void enable_dev(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 506 | { |
| 507 | /* Set the operations if it is a special bus type */ |
| 508 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 509 | dev->ops = &pci_domain_ops; |
| 510 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 511 | dev->ops = &cpu_bus_ops; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | struct chip_operations northbridge_intel_haswell_ops = { |
| 516 | CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") |
| 517 | .enable_dev = enable_dev, |
| 518 | }; |