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Edward O'Callaghan1f9653a2014-07-14 16:31:25 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100015 */
16
17#include <arch/io.h>
Kyösti Mälkki3855c012019-03-03 08:45:19 +020018#include <device/pnp_ops.h>
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100019
20#include "it8772f.h"
21
22/* NOTICE: This file is deprecated, use ite/common instead */
23
Edward O'Callaghan85836c22014-07-09 20:26:25 +100024void it8772f_enter_conf(pnp_devfn_t dev)
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100025{
26 u16 port = dev >> 8;
27
28 outb(0x87, port);
29 outb(0x01, port);
30 outb(0x55, port);
31 outb((port == 0x4e) ? 0xaa : 0x55, port);
32}
33
Edward O'Callaghan85836c22014-07-09 20:26:25 +100034void it8772f_exit_conf(pnp_devfn_t dev)
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100035{
Felix Held6c244bd2019-10-07 18:47:29 +020036 pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100037}
38
39/* Set AC resume to be up to the Southbridge */
Edward O'Callaghan85836c22014-07-09 20:26:25 +100040void it8772f_ac_resume_southbridge(pnp_devfn_t dev)
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100041{
42 it8772f_enter_conf(dev);
Felix Held6c244bd2019-10-07 18:47:29 +020043 pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC);
44 pnp_write_config(dev, 0xf4, 0x60);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100045 it8772f_exit_conf(dev);
46}
47
48/* Configure a set of GPIOs */
Edward O'Callaghan85836c22014-07-09 20:26:25 +100049void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity,
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100050 u8 pullup, u8 output, u8 enable)
51{
52 set--; /* Set 1 is offset 0 */
53 it8772f_enter_conf(dev);
Felix Held6c244bd2019-10-07 18:47:29 +020054 pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100055 if (set < 5) {
Felix Held6c244bd2019-10-07 18:47:29 +020056 pnp_write_config(dev, GPIO_REG_SELECT(set), select);
57 pnp_write_config(dev, GPIO_REG_ENABLE(set), enable);
58 pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100059 }
Felix Held6c244bd2019-10-07 18:47:29 +020060 pnp_write_config(dev, GPIO_REG_OUTPUT(set), output);
61 pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup);
Edward O'Callaghan1f9653a2014-07-14 16:31:25 +100062 it8772f_exit_conf(dev);
63}
david80ef7b72015-01-19 17:11:36 +080064
65/* Configure LED GPIOs */
66void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup,
67 u8 output, u8 enable, u8 led_pin_map, u8 led_freq)
68{
69 set--; /* Set 1 is offset 0 */
70 it8772f_enter_conf(dev);
Felix Held6c244bd2019-10-07 18:47:29 +020071 pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
david80ef7b72015-01-19 17:11:36 +080072 if (set < 5) {
Felix Held6c244bd2019-10-07 18:47:29 +020073 pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map);
74 pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq);
75 pnp_write_config(dev, GPIO_REG_SELECT(set), select);
76 pnp_write_config(dev, GPIO_REG_ENABLE(set), enable);
77 pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity);
david80ef7b72015-01-19 17:11:36 +080078 }
Felix Held6c244bd2019-10-07 18:47:29 +020079 pnp_write_config(dev, GPIO_REG_OUTPUT(set), output);
80 pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup);
david80ef7b72015-01-19 17:11:36 +080081 it8772f_exit_conf(dev);
82}