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Varadarajan Narayanana6935c22016-03-02 16:57:10 +05301/*
2 * Copyright (c) 2012 The Linux Foundation. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above
10 * copyright notice, this list of conditions and the following
11 * disclaimer in the documentation and/or other materials provided
12 * with the distribution.
13 * * Neither the name of The Linux Foundation nor the names of its
14 * contributors may be used to endorse or promote products derived
15 * from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
24 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
26 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
27 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
Kyösti Mälkki13f66502019-03-03 08:01:05 +020030#include <device/mmio.h>
Furquan Shaikhc28984d2016-11-20 21:04:00 -080031#include <console/console.h>
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053032#include <delay.h>
33#include <gpio.h>
34#include <soc/iomap.h>
35#include <soc/spi.h>
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053036
Varadarajan Narayanan25967642016-03-08 15:02:56 +053037static const struct blsp_spi spi_reg[] = {
38 /* BLSP0 registers for SPI interface */
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053039 {
Varadarajan Narayanan25967642016-03-08 15:02:56 +053040 BLSP0_SPI_CONFIG_REG,
41 BLSP0_SPI_IO_CONTROL_REG,
42 BLSP0_SPI_ERROR_FLAGS_REG,
43 BLSP0_SPI_ERROR_FLAGS_EN_REG,
44 BLSP0_QUP_CONFIG_REG,
45 BLSP0_QUP_ERROR_FLAGS_REG,
46 BLSP0_QUP_ERROR_FLAGS_EN_REG,
47 BLSP0_QUP_OPERATIONAL_REG,
48 BLSP0_QUP_IO_MODES_REG,
49 BLSP0_QUP_STATE_REG,
50 BLSP0_QUP_INPUT_FIFOc_REG(0),
51 BLSP0_QUP_OUTPUT_FIFOc_REG(0),
52 BLSP0_QUP_MX_INPUT_COUNT_REG,
53 BLSP0_QUP_MX_OUTPUT_COUNT_REG,
54 BLSP0_QUP_SW_RESET_REG,
55 0,
56 0,
57 BLSP0_QUP_OPERATIONAL_MASK,
58 BLSP0_SPI_DEASSERT_WAIT_REG,
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053059 },
Varadarajan Narayanan25967642016-03-08 15:02:56 +053060 /* BLSP1 registers for SPI interface */
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053061 {
Varadarajan Narayanan25967642016-03-08 15:02:56 +053062 BLSP1_SPI_CONFIG_REG,
63 BLSP1_SPI_IO_CONTROL_REG,
64 BLSP1_SPI_ERROR_FLAGS_REG,
65 BLSP1_SPI_ERROR_FLAGS_EN_REG,
66 BLSP1_QUP_CONFIG_REG,
67 BLSP1_QUP_ERROR_FLAGS_REG,
68 BLSP1_QUP_ERROR_FLAGS_EN_REG,
69 BLSP1_QUP_OPERATIONAL_REG,
70 BLSP1_QUP_IO_MODES_REG,
71 BLSP1_QUP_STATE_REG,
72 BLSP1_QUP_INPUT_FIFOc_REG(0),
73 BLSP1_QUP_OUTPUT_FIFOc_REG(0),
74 BLSP1_QUP_MX_INPUT_COUNT_REG,
75 BLSP1_QUP_MX_OUTPUT_COUNT_REG,
76 BLSP1_QUP_SW_RESET_REG,
77 0,
78 0,
79 BLSP1_QUP_OPERATIONAL_MASK,
80 BLSP1_SPI_DEASSERT_WAIT_REG,
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053081 },
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053082};
83
Varadarajan Narayanan25967642016-03-08 15:02:56 +053084static int check_bit_state(void *reg_addr, int mask,
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053085 int val, int us_delay)
86{
87 unsigned int count = TIMEOUT_CNT;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053088
Varadarajan Narayanan25967642016-03-08 15:02:56 +053089 while ((read32(reg_addr) & mask) != val) {
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053090 count--;
91 if (count == 0)
92 return -ETIMEDOUT;
93 udelay(us_delay);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +053094 }
95
96 return SUCCESS;
97}
98
99/*
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530100 * Check whether QUPn State is valid
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530101 */
102static int check_qup_state_valid(struct ipq_spi_slave *ds)
103{
104
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530105 return check_bit_state(ds->regs->qup_state, QUP_STATE_VALID_MASK,
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530106 QUP_STATE_VALID, 1);
107
108}
109
110/*
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530111 * Configure QUPn Core state
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530112 */
113static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state)
114{
115 uint32_t val;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530116 int ret = SUCCESS;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530117
118 ret = check_qup_state_valid(ds);
119 if (ret != SUCCESS)
120 return ret;
121
122 switch (state) {
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530123 case QUP_STATE_RUN:
124 /* Set the state to RUN */
125 val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK)
126 | QUP_STATE_RUN);
127 write32(ds->regs->qup_state, val);
128 ret = check_qup_state_valid(ds);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530129 break;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530130 case QUP_STATE_RESET:
131 /* Set the state to RESET */
132 val = ((read32(ds->regs->qup_state) & ~QUP_STATE_MASK)
133 | QUP_STATE_RESET);
134 write32(ds->regs->qup_state, val);
135 ret = check_qup_state_valid(ds);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530136 break;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530137 default:
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530138 printk(BIOS_ERR, "unsupported QUP SPI state : %d\n", state);
139 ret = -EINVAL;
140 break;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530141 }
142
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530143 return ret;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530144}
145
146/*
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530147 * Set QUPn SPI Mode
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530148 */
149static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode)
150{
151 unsigned int clk_idle_state;
152 unsigned int input_first_mode;
153 uint32_t val;
154
155 switch (mode) {
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530156 case SPI_MODE0:
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530157 clk_idle_state = 0;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530158 input_first_mode = SPI_CONFIG_INPUT_FIRST;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530159 break;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530160 case SPI_MODE1:
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530161 clk_idle_state = 0;
162 input_first_mode = 0;
163 break;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530164 case SPI_MODE2:
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530165 clk_idle_state = 1;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530166 input_first_mode = SPI_CONFIG_INPUT_FIRST;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530167 break;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530168 case SPI_MODE3:
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530169 clk_idle_state = 1;
170 input_first_mode = 0;
171 break;
172 default:
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530173 printk(BIOS_ERR, "unsupported spi mode : %d\n", mode);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530174 return;
175 }
176
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530177 val = read32(ds->regs->spi_config);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530178 val |= input_first_mode;
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530179 write32(ds->regs->spi_config, val);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530180
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530181 val = read32(ds->regs->io_control);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530182 if (clk_idle_state)
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530183 val |= SPI_IO_CTRL_CLOCK_IDLE_HIGH;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530184 else
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530185 val &= ~SPI_IO_CTRL_CLOCK_IDLE_HIGH;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530186
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530187 write32(ds->regs->io_control, val);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530188}
189
190/*
191 * Reset entire QUP and all mini cores
192 */
193static void spi_reset(struct ipq_spi_slave *ds)
194{
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530195 write32(ds->regs->qup_sw_reset, 0x1);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530196 udelay(5);
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530197 check_qup_state_valid(ds);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530198}
199
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530200static struct ipq_spi_slave spi_slave_pool[2];
201
Furquan Shaikh36b81af2016-12-01 01:02:44 -0800202static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave)
203{
204 struct ipq_spi_slave *ds;
205 size_t i;
206
207 for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) {
208 ds = spi_slave_pool + i;
209
210 if (!ds->allocated)
211 continue;
212
213 if ((ds->slave.bus == slave->bus) &&
214 (ds->slave.cs == slave->cs))
215 return ds;
216 }
217
218 return NULL;
219}
220
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530221/*
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530222 * BLSP QUPn SPI Hardware Initialisation
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530223 */
224static int spi_hw_init(struct ipq_spi_slave *ds)
225{
226 int ret;
227
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530228 ds->initialized = 0;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530229
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530230 /* QUPn module configuration */
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530231 spi_reset(ds);
232
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530233 /* Set the QUPn state */
234 ret = config_spi_state(ds, QUP_STATE_RESET);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530235 if (ret)
236 return ret;
237
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530238 /*
239 * Configure Mini core to SPI core with Input Output enabled,
240 * SPI master, N = 8 bits
241 */
Julius Werner55009af2019-12-02 22:03:27 -0800242 clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530243 QUP_CONF_INPUT_MSK |
244 QUP_CONF_OUTPUT_MSK |
245 QUP_CONF_N_MASK,
246 QUP_CONFIG_MINI_CORE_SPI |
247 QUP_CONF_INPUT_ENA |
248 QUP_CONF_OUTPUT_ENA |
249 QUP_CONF_N_SPI_8_BIT_WORD);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530250
251 /*
252 * Configure Input first SPI protocol,
253 * SPI master mode and no loopback
254 */
Julius Werner55009af2019-12-02 22:03:27 -0800255 clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530256 SPI_CONFIG_NO_SLAVE_OPER_MSK,
257 SPI_CONFIG_NO_LOOP_BACK |
258 SPI_CONFIG_NO_SLAVE_OPER);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530259
260 /*
261 * Configure SPI IO Control Register
262 * CLK_ALWAYS_ON = 0
263 * MX_CS_MODE = 0
264 * NO_TRI_STATE = 1
265 */
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530266 write32(ds->regs->io_control, SPI_IO_CTRL_CLK_ALWAYS_ON |
267 SPI_IO_CTRL_NO_TRI_STATE);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530268
269 /*
270 * Configure SPI IO Modes.
271 * OUTPUT_BIT_SHIFT_EN = 1
272 * INPUT_MODE = Block Mode
273 * OUTPUT MODE = Block Mode
274 */
Julius Werner55009af2019-12-02 22:03:27 -0800275 clrsetbits32(ds->regs->qup_io_modes,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530276 QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
277 QUP_IO_MODES_INPUT_MODE_MSK |
278 QUP_IO_MODES_OUTPUT_MODE_MSK,
279 QUP_IO_MODES_OUTPUT_BIT_SHIFT_EN |
280 QUP_IO_MODES_INPUT_BLOCK_MODE |
281 QUP_IO_MODES_OUTPUT_BLOCK_MODE);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530282
283 spi_set_mode(ds, ds->mode);
284
285 /* Disable Error mask */
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530286 write32(ds->regs->error_flags_en, 0);
287 write32(ds->regs->qup_error_flags_en, 0);
288
289 write32(ds->regs->qup_deassert_wait, 0);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530290
291 ds->initialized = 1;
292
293 return SUCCESS;
294}
295
Furquan Shaikh94f86992016-12-01 07:12:32 -0800296static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530297{
298 struct ipq_spi_slave *ds = to_ipq_spi(slave);
299 unsigned int ret;
300
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530301 ret = spi_hw_init(ds);
302 if (ret)
303 return -EIO;
304
305 return SUCCESS;
306}
307
Furquan Shaikh94f86992016-12-01 07:12:32 -0800308static void spi_ctrlr_release_bus(const struct spi_slave *slave)
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530309{
310 struct ipq_spi_slave *ds = to_ipq_spi(slave);
311
312 /* Reset the SPI hardware */
313 spi_reset(ds);
314 ds->initialized = 0;
315}
316
Furquan Shaikh0dba0252016-11-30 04:34:22 -0800317static void write_force_cs(const struct spi_slave *slave, int assert)
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530318{
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530319 struct ipq_spi_slave *ds = to_ipq_spi(slave);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530320
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530321 if (assert)
Julius Werner55009af2019-12-02 22:03:27 -0800322 clrsetbits32(ds->regs->io_control,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530323 SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN);
324 else
Julius Werner55009af2019-12-02 22:03:27 -0800325 clrsetbits32(ds->regs->io_control,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530326 SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530327
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530328 return;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530329}
330
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530331/*
332 * Function to write data to OUTPUT FIFO
333 */
334static void spi_write_byte(struct ipq_spi_slave *ds, unsigned char data)
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530335{
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530336 /* Wait for space in the FIFO */
337 while ((read32(ds->regs->qup_operational) & OUTPUT_FIFO_FULL))
338 udelay(1);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530339
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530340 /* Write the byte of data */
341 write32(ds->regs->qup_output_fifo, data);
342}
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530343
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530344/*
345 * Function to read data from Input FIFO
346 */
347static unsigned char spi_read_byte(struct ipq_spi_slave *ds)
348{
349 /* Wait for Data in FIFO */
350 while (!(read32(ds->regs->qup_operational) & INPUT_FIFO_NOT_EMPTY))
351 udelay(1);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530352
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530353 /* Read a byte of data */
354 return read32(ds->regs->qup_input_fifo) & 0xff;
355}
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530356
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530357/*
358 * Function to check wheather Input or Output FIFO
359 * has data to be serviced
360 */
361static int check_fifo_status(void *reg_addr)
362{
363 unsigned int count = TIMEOUT_CNT;
364 unsigned int status_flag;
365 unsigned int val;
366
367 do {
368 val = read32(reg_addr);
369 count--;
370 if (count == 0)
371 return -ETIMEDOUT;
372 status_flag = ((val & OUTPUT_SERVICE_FLAG) |
373 (val & INPUT_SERVICE_FLAG));
374 } while (!status_flag);
375
376 return SUCCESS;
377}
378
379/*
380 * Function to configure Input and Output enable/disable
381 */
382static void enable_io_config(struct ipq_spi_slave *ds,
383 uint32_t write_cnt, uint32_t read_cnt)
384{
385
386 if (write_cnt) {
Julius Werner55009af2019-12-02 22:03:27 -0800387 clrsetbits32(ds->regs->qup_config,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530388 QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
389 } else {
Julius Werner55009af2019-12-02 22:03:27 -0800390 clrsetbits32(ds->regs->qup_config,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530391 QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530392 }
393
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530394 if (read_cnt) {
Julius Werner55009af2019-12-02 22:03:27 -0800395 clrsetbits32(ds->regs->qup_config,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530396 QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
397 } else {
Julius Werner55009af2019-12-02 22:03:27 -0800398 clrsetbits32(ds->regs->qup_config,
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530399 QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
400 }
401
402 return;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530403}
404
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530405/*
406 * Function to read bytes number of data from the Input FIFO
407 */
408static int __blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer,
409 unsigned int bytes)
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530410{
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530411 uint32_t val;
412 unsigned int i;
413 unsigned int fifo_count;
414 int ret = SUCCESS;
415 int state_config;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530416
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530417 /* Configure no of bytes to read */
418 state_config = config_spi_state(ds, QUP_STATE_RESET);
419 if (state_config)
420 return state_config;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530421
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530422 /* Configure input and output enable */
423 enable_io_config(ds, 0, bytes);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530424
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530425 write32(ds->regs->qup_mx_input_count, bytes);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530426
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530427 state_config = config_spi_state(ds, QUP_STATE_RUN);
428 if (state_config)
429 return state_config;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530430
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530431 while (bytes) {
432 ret = check_fifo_status(ds->regs->qup_operational);
433 if (ret != SUCCESS)
434 goto out;
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530435
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530436 val = read32(ds->regs->qup_operational);
437 if (val & INPUT_SERVICE_FLAG) {
438 /*
439 * acknowledge to hw that software will
440 * read input data
441 */
442 val &= INPUT_SERVICE_FLAG;
443 write32(ds->regs->qup_operational, val);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530444
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530445 fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ?
446 SPI_INPUT_BLOCK_SIZE : bytes);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530447
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530448 for (i = 0; i < fifo_count; i++) {
449 *data_buffer = spi_read_byte(ds);
450 data_buffer++;
451 bytes--;
452 }
453 }
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530454 }
455
456out:
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530457 /*
458 * Put the SPI Core back in the Reset State
459 * to end the transfer
460 */
461 (void)config_spi_state(ds, QUP_STATE_RESET);
462 return ret;
463}
464
465static int blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer,
466 unsigned int bytes)
467{
468 int length, ret;
469
470 while (bytes) {
471 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
472
473 ret = __blsp_spi_read(ds, data_buffer, length);
474 if (ret != SUCCESS)
475 return ret;
476
477 data_buffer += length;
478 bytes -= length;
479 }
480
481 return 0;
482}
483
484/*
485 * Function to write data to the Output FIFO
486 */
487static int __blsp_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer,
488 unsigned int bytes)
489{
490 uint32_t val;
491 unsigned int i;
492 unsigned int write_len = bytes;
493 unsigned int read_len = bytes;
494 unsigned int fifo_count;
495 int ret = SUCCESS;
496 int state_config;
497
498 state_config = config_spi_state(ds, QUP_STATE_RESET);
499 if (state_config)
500 return state_config;
501
502 /* No of bytes to be written in Output FIFO */
503 write32(ds->regs->qup_mx_output_count, bytes);
504 write32(ds->regs->qup_mx_input_count, bytes);
505 state_config = config_spi_state(ds, QUP_STATE_RUN);
506 if (state_config)
507 return state_config;
508
509 /* Configure input and output enable */
510 enable_io_config(ds, write_len, read_len);
511
512 /*
513 * read_len considered to ensure that we read the dummy data for the
514 * write we performed. This is needed to ensure with WR-RD transaction
515 * to get the actual data on the subsequent read cycle that happens
516 */
517 while (write_len || read_len) {
518
519 ret = check_fifo_status(ds->regs->qup_operational);
520 if (ret != SUCCESS)
521 goto out;
522
523 val = read32(ds->regs->qup_operational);
524 if (val & OUTPUT_SERVICE_FLAG) {
525 /*
526 * acknowledge to hw that software will write
527 * expected output data
528 */
529 val &= OUTPUT_SERVICE_FLAG;
530 write32(ds->regs->qup_operational, val);
531
532 if (write_len > SPI_OUTPUT_BLOCK_SIZE)
533 fifo_count = SPI_OUTPUT_BLOCK_SIZE;
534 else
535 fifo_count = write_len;
536
537 for (i = 0; i < fifo_count; i++) {
538 /* Write actual data to output FIFO */
539 spi_write_byte(ds, *cmd_buffer);
540 cmd_buffer++;
541 write_len--;
542 }
543 }
544 if (val & INPUT_SERVICE_FLAG) {
545 /*
546 * acknowledge to hw that software
547 * will read input data
548 */
549 val &= INPUT_SERVICE_FLAG;
550 write32(ds->regs->qup_operational, val);
551
552 if (read_len > SPI_INPUT_BLOCK_SIZE)
553 fifo_count = SPI_INPUT_BLOCK_SIZE;
554 else
555 fifo_count = read_len;
556
557 for (i = 0; i < fifo_count; i++) {
558 /* Read dummy data for the data written */
559 (void)spi_read_byte(ds);
560
561 /* Decrement the read count after reading the
562 * dummy data from the device. This is to make
563 * sure we read dummy data before we write the
564 * data to fifo
565 */
566 read_len--;
567 }
568 }
569 }
570
571out:
572 /*
573 * Put the SPI Core back in the Reset State
574 * to end the transfer
575 */
576 (void)config_spi_state(ds, QUP_STATE_RESET);
577
578 return ret;
579}
580
581static int blsp_spi_write(struct ipq_spi_slave *ds, u8 *cmd_buffer,
582 unsigned int bytes)
583{
584 int length, ret;
585
586 while (bytes) {
587 length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
588
589 ret = __blsp_spi_write(ds, cmd_buffer, length);
590 if (ret != SUCCESS)
591 return ret;
592
593 cmd_buffer += length;
594 bytes -= length;
595 }
596
597 return 0;
598}
599
600/*
601 * This function is invoked with either tx_buf or rx_buf.
602 * Calling this function with both null does a chip select change.
603 */
Furquan Shaikh94f86992016-12-01 07:12:32 -0800604static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
605 size_t out_bytes, void *din, size_t in_bytes)
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530606{
607 struct ipq_spi_slave *ds = to_ipq_spi(slave);
608 u8 *txp = (u8 *)dout;
609 u8 *rxp = (u8 *)din;
610 int ret;
611
Aaron Durbin9a1bb362018-04-19 16:58:13 -0600612 /* Driver implementation does not support full duplex. */
613 if (dout && din)
614 return -1;
615
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530616 ret = config_spi_state(ds, QUP_STATE_RESET);
617 if (ret != SUCCESS)
618 return ret;
619
620 write_force_cs(slave, 1);
621
622 if (dout != NULL) {
623 ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes);
624 if (ret != SUCCESS)
625 goto out;
626 }
627
628 if (din != NULL) {
629 ret = blsp_spi_read(ds, rxp, in_bytes);
630 if (ret != SUCCESS)
631 goto out;
632 }
633
634out:
635 write_force_cs(slave, 0);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530636
637 /*
638 * Put the SPI Core back in the Reset State
639 * to end the transfer
640 */
Varadarajan Narayanan25967642016-03-08 15:02:56 +0530641 (void)config_spi_state(ds, QUP_STATE_RESET);
Varadarajan Narayanana6935c22016-03-02 16:57:10 +0530642
643 return ret;
644}
Furquan Shaikh94f86992016-12-01 07:12:32 -0800645
Furquan Shaikhe424a592017-05-18 14:40:58 -0700646static int spi_ctrlr_setup(const struct spi_slave *slave)
Furquan Shaikh94f86992016-12-01 07:12:32 -0800647{
648 struct ipq_spi_slave *ds = NULL;
649 int i;
Julius Werner7c712bb2019-05-01 16:51:20 -0700650 int bus = slave->bus;
651 int cs = slave->cs;
Furquan Shaikh94f86992016-12-01 07:12:32 -0800652
653 if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI)
654 || ((bus == BLSP0_SPI) && (cs > 2))
655 || ((bus == BLSP1_SPI) && (cs > 0))) {
656 printk(BIOS_ERR,
657 "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) "
Elyes HAOUAS88607a42018-10-05 10:36:45 +0200658 "or chipselect\n", bus);
Furquan Shaikh94f86992016-12-01 07:12:32 -0800659 return -1;
660 }
661
662 for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) {
663 if (spi_slave_pool[i].allocated)
664 continue;
665 ds = spi_slave_pool + i;
666
Furquan Shaikhe424a592017-05-18 14:40:58 -0700667 ds->slave.bus = bus;
668 ds->slave.cs = cs;
Furquan Shaikh94f86992016-12-01 07:12:32 -0800669 ds->regs = &spi_reg[bus];
670
671 /*
672 * TODO(vbendeb):
673 * hardcoded frequency and mode - we might need to find a way
674 * to configure this
675 */
676 ds->freq = 10000000;
677 ds->mode = SPI_MODE3;
678 ds->allocated = 1;
679
680 return 0;
681 }
682
683 printk(BIOS_ERR, "SPI error: all %d pools busy\n", i);
684 return -1;
685}
Furquan Shaikhe424a592017-05-18 14:40:58 -0700686
687static const struct spi_ctrlr spi_ctrlr = {
688 .setup = spi_ctrlr_setup,
689 .claim_bus = spi_ctrlr_claim_bus,
690 .release_bus = spi_ctrlr_release_bus,
691 .xfer = spi_ctrlr_xfer,
Furquan Shaikhe424a592017-05-18 14:40:58 -0700692 .max_xfer_size = MAX_PACKET_COUNT,
693};
694
695const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
696 {
697 .ctrlr = &spi_ctrlr,
698 .bus_start = BLSP0_SPI,
699 .bus_end = BLSP1_SPI,
700 },
701};
702
703const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);