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Subrata Banik01ae11b2017-03-04 23:32:41 +05301/*
2 * This file is part of the coreboot project.
3 *
Subrata Banikb6df6b02020-01-03 15:29:02 +05304 * Copyright (C) 2017-2020 Intel Corporation.
Werner Zehd12530c2018-12-14 13:09:12 +01005 * Copyright (C) 2019 Siemens AG
Subrata Banik01ae11b2017-03-04 23:32:41 +05306 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Subrata Banik7609c652017-05-19 14:50:09 +053017#include <cbmem.h>
Subrata Banikb6df6b02020-01-03 15:29:02 +053018#include <console/console.h>
Subrata Banik7609c652017-05-19 14:50:09 +053019#include <device/device.h>
20#include <device/pci.h>
21#include <device/pci_ids.h>
Werner Zehd12530c2018-12-14 13:09:12 +010022#include <intelblocks/acpi.h>
Subrata Banikb6df6b02020-01-03 15:29:02 +053023#include <intelblocks/cfg.h>
Subrata Banik01ae11b2017-03-04 23:32:41 +053024#include <intelblocks/systemagent.h>
Lijian Zhao357e5522019-04-11 13:07:00 -070025#include <smbios.h>
Subrata Banik7609c652017-05-19 14:50:09 +053026#include <soc/iomap.h>
Subrata Banik01ae11b2017-03-04 23:32:41 +053027#include <soc/pci_devs.h>
Subrata Banik7609c652017-05-19 14:50:09 +053028#include <soc/systemagent.h>
29#include "systemagent_def.h"
Subrata Banik01ae11b2017-03-04 23:32:41 +053030
Subrata Banik7609c652017-05-19 14:50:09 +053031/* SoC override function */
Aaron Durbin64031672018-04-21 14:45:32 -060032__weak void soc_systemagent_init(struct device *dev)
Subrata Banik01ae11b2017-03-04 23:32:41 +053033{
Subrata Banik7609c652017-05-19 14:50:09 +053034 /* no-op */
Subrata Banik01ae11b2017-03-04 23:32:41 +053035}
36
Aaron Durbin64031672018-04-21 14:45:32 -060037__weak void soc_add_fixed_mmio_resources(struct device *dev,
Subrata Banik7609c652017-05-19 14:50:09 +053038 int *resource_cnt)
39{
40 /* no-op */
41}
42
Aaron Durbin64031672018-04-21 14:45:32 -060043__weak int soc_get_uncore_prmmr_base_and_mask(uint64_t *base,
Pratik Prajapati82cdfa72017-08-28 14:48:55 -070044 uint64_t *mask)
45{
46 /* return failure for this dummy API */
47 return -1;
48}
49
Werner Zehd12530c2018-12-14 13:09:12 +010050__weak unsigned long sa_write_acpi_tables(struct device *dev,
51 unsigned long current,
52 struct acpi_rsdp *rsdp)
53{
54 return current;
55}
56
Subrata Banik7609c652017-05-19 14:50:09 +053057/*
Subrata Banikb6df6b02020-01-03 15:29:02 +053058 * This function will get above 4GB mmio enable config specific to soc.
59 *
60 * Return values:
61 * 0 = Above 4GB memory is not enable
62 * 1 = Above 4GB memory is enable
63 */
64static int get_enable_above_4GB_mmio(void)
65{
66 const struct soc_intel_common_config *common_config;
67 common_config = chip_get_common_soc_structure();
68
69 return common_config->enable_above_4GB_mmio;
70}
71
72/* Fill MMIO resource above 4GB into GNVS */
73void sa_fill_gnvs(global_nvs_t *gnvs)
74{
75 if (get_enable_above_4GB_mmio()) {
76 gnvs->e4gm = 1;
77 gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS;
78 gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
79 printk(BIOS_DEBUG,
80 "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n",
81 gnvs->a4gb, gnvs->a4gs);
82 }
83}
84
85/*
Subrata Banik7609c652017-05-19 14:50:09 +053086 * Add all known fixed MMIO ranges that hang off the host bridge/memory
87 * controller device.
88 */
89void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt,
90 const struct sa_mmio_descriptor *sa_fixed_resources, size_t count)
91{
92 int i;
93 int index = *resource_cnt;
94
95 for (i = 0; i < count; i++) {
96 uintptr_t base;
97 size_t size;
98
99 size = sa_fixed_resources[i].size;
100 base = sa_fixed_resources[i].base;
101
102 mmio_resource(dev, index++, base / KiB, size / KiB);
103 }
104
105 *resource_cnt = index;
106}
107
108/*
109 * DRAM memory mapped register
110 *
111 * TOUUD: This 64 bit register defines the Top of Upper Usable DRAM
112 * TOLUD: This 32 bit register defines the Top of Low Usable DRAM
113 * BGSM: This register contains the base address of stolen DRAM memory for GTT
114 * TSEG: This register contains the base address of TSEG DRAM memory
115 */
116static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = {
117 { TOUUD, true, "TOUUD" },
118 { TOLUD, false, "TOLUD" },
119 { BGSM, false, "BGSM" },
120 { TSEG, false, "TSEG" },
121};
122
123/* Read DRAM memory map register value through PCI configuration space */
Elyes HAOUAS4a131262018-09-16 17:35:48 +0200124static void sa_read_map_entry(struct device *dev,
Subrata Banik7609c652017-05-19 14:50:09 +0530125 const struct sa_mem_map_descriptor *entry, uint64_t *result)
126{
127 uint64_t value = 0;
128
129 if (entry->is_64_bit) {
130 value = pci_read_config32(dev, entry->reg + 4);
131 value <<= 32;
132 }
133
134 value |= pci_read_config32(dev, entry->reg);
135 /* All registers are on a 1MiB granularity. */
136 value = ALIGN_DOWN(value, 1 * MiB);
137
138 *result = value;
139}
140
141static void sa_get_mem_map(struct device *dev, uint64_t *values)
142{
143 int i;
144 for (i = 0; i < MAX_MAP_ENTRIES; i++)
145 sa_read_map_entry(dev, &sa_memory_map[i], &values[i]);
146}
147
148/*
Subrata Banik7609c652017-05-19 14:50:09 +0530149 * These are the host memory ranges that should be added:
150 * - 0 -> 0xa0000: cacheable
151 * - 0xc0000 -> top_of_ram : cacheable
Michael Niewöhner40f893e2019-10-21 18:58:04 +0200152 * - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved
Subrata Banik7609c652017-05-19 14:50:09 +0530153 * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
154 * - 4GiB -> TOUUD: cacheable
155 *
156 * The default SMRAM space is reserved so that the range doesn't
157 * have to be saved during S3 Resume. Once marked reserved the OS
158 * cannot use the memory. This is a bit of an odd place to reserve
159 * the region, but the CPU devices don't have dev_ops->read_resources()
160 * called on them.
161 *
162 * The range 0xa0000 -> 0xc0000 does not have any resources
163 * associated with it to handle legacy VGA memory. If this range
164 * is not omitted the mtrr code will setup the area as cacheable
165 * causing VGA access to not work.
166 *
167 * The TSEG region is mapped as cacheable so that one can perform
168 * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
169 * precedence over the existing MTRRs covering this region.
170 *
171 * It should be noted that cacheable entry types need to be added in
172 * order. The reason is that the current MTRR code assumes this and
173 * falls over itself if it isn't.
174 *
175 * The resource index starts low and should not meet or exceed
176 * PCI_BASE_ADDRESS_0.
177 */
178static void sa_add_dram_resources(struct device *dev, int *resource_count)
179{
180 uintptr_t base_k, touud_k;
Michael Niewöhner40f893e2019-10-21 18:58:04 +0200181 size_t size_k;
Subrata Banik7609c652017-05-19 14:50:09 +0530182 uint64_t sa_map_values[MAX_MAP_ENTRIES];
183 uintptr_t top_of_ram;
184 int index = *resource_count;
185
Subrata Banik7609c652017-05-19 14:50:09 +0530186 top_of_ram = (uintptr_t)cbmem_top();
187
188 /* 0 - > 0xa0000 */
189 base_k = 0;
190 size_k = (0xa0000 / KiB) - base_k;
191 ram_resource(dev, index++, base_k, size_k);
192
193 /* 0xc0000 -> top_of_ram */
194 base_k = 0xc0000 / KiB;
195 size_k = (top_of_ram / KiB) - base_k;
196 ram_resource(dev, index++, base_k, size_k);
197
198 sa_get_mem_map(dev, &sa_map_values[0]);
199
Michael Niewöhner40f893e2019-10-21 18:58:04 +0200200 /* top_of_ram -> BGSM */
Subrata Banik7609c652017-05-19 14:50:09 +0530201 base_k = top_of_ram;
Subrata Banik7609c652017-05-19 14:50:09 +0530202 size_k = sa_map_values[SA_BGSM_REG] - base_k;
203 reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB);
204
205 /* BGSM -> TOLUD */
206 base_k = sa_map_values[SA_BGSM_REG];
207 size_k = sa_map_values[SA_TOLUD_REG] - base_k;
208 mmio_resource(dev, index++, base_k / KiB, size_k / KiB);
209
210 /* 4GiB -> TOUUD */
211 base_k = 4 * (GiB / KiB); /* 4GiB */
212 touud_k = sa_map_values[SA_TOUUD_REG] / KiB;
213 size_k = touud_k - base_k;
214 if (touud_k > base_k)
215 ram_resource(dev, index++, base_k, size_k);
216
217 /*
218 * Reserve everything between A segment and 1MB:
219 *
220 * 0xa0000 - 0xbffff: legacy VGA
221 * 0xc0000 - 0xfffff: RAM
222 */
223 mmio_resource(dev, index++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
224 reserved_ram_resource(dev, index++, 0xc0000 / KiB,
225 (1*MiB - 0xc0000) / KiB);
226
227 *resource_count = index;
228}
229
230static bool is_imr_enabled(uint32_t imr_base_reg)
231{
232 return !!(imr_base_reg & (1 << 31));
233}
234
Elyes HAOUAS4a131262018-09-16 17:35:48 +0200235static void imr_resource(struct device *dev, int idx, uint32_t base,
236 uint32_t mask)
Subrata Banik7609c652017-05-19 14:50:09 +0530237{
238 uint32_t base_k, size_k;
239 /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */
240 base_k = (base & 0x0fffffff);
241 /* Bits 28:0 encode the AND mask used for comparison, in KiB. */
242 size_k = ((~mask & 0x0fffffff) + 1);
243 /*
244 * IMRs sit in lower DRAM. Mark them cacheable, otherwise we run
245 * out of MTRRs. Memory reserved by IMRs is not usable for host
246 * so mark it reserved.
247 */
248 reserved_ram_resource(dev, idx, base_k, size_k);
249}
250
251/*
252 * Add IMR ranges that hang off the host bridge/memory
253 * controller device in case CONFIG_SA_ENABLE_IMR is selected by SoC.
254 */
255static void sa_add_imr_resources(struct device *dev, int *resource_cnt)
256{
257 size_t i, imr_offset;
258 uint32_t base, mask;
259 int index = *resource_cnt;
260
261 for (i = 0; i < MCH_NUM_IMRS; i++) {
262 imr_offset = i * MCH_IMR_PITCH;
263 base = MCHBAR32(imr_offset + MCH_IMR0_BASE);
264 mask = MCHBAR32(imr_offset + MCH_IMR0_MASK);
265
266 if (is_imr_enabled(base))
267 imr_resource(dev, index++, base, mask);
268 }
269
270 *resource_cnt = index;
271}
272
273static void systemagent_read_resources(struct device *dev)
274{
275 int index = 0;
276
277 /* Read standard PCI resources. */
278 pci_dev_read_resources(dev);
279
280 /* Add all fixed MMIO resources. */
281 soc_add_fixed_mmio_resources(dev, &index);
282 /* Calculate and add DRAM resources. */
283 sa_add_dram_resources(dev, &index);
Julius Wernercd49cce2019-03-05 16:53:33 -0800284 if (CONFIG(SA_ENABLE_IMR))
Subrata Banik7609c652017-05-19 14:50:09 +0530285 /* Add the isolated memory ranges (IMRs). */
286 sa_add_imr_resources(dev, &index);
287}
288
Lijian Zhao357e5522019-04-11 13:07:00 -0700289#if CONFIG(GENERATE_SMBIOS_TABLES)
290static int sa_smbios_write_type_16(struct device *dev, int *handle,
291 unsigned long *current)
292{
293 struct smbios_type16 *t = (struct smbios_type16 *)*current;
294 int len = sizeof(struct smbios_type16);
295
296 struct memory_info *meminfo;
297 meminfo = cbmem_find(CBMEM_ID_MEMINFO);
298 if (meminfo == NULL)
299 return 0; /* can't find mem info in cbmem */
300
301 memset(t, 0, sizeof(struct smbios_type16));
302 t->type = SMBIOS_PHYS_MEMORY_ARRAY;
303 t->handle = *handle;
304 t->length = len - 2;
305 t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
306 t->use = MEMORY_ARRAY_USE_SYSTEM;
307 /* TBD, meminfo hob have information about ECC */
308 t->memory_error_correction = MEMORY_ARRAY_ECC_NONE;
309 /* no error information handle available */
310 t->memory_error_information_handle = 0xFFFE;
311 t->maximum_capacity = 32 * (GiB / KiB); /* 32GB as default */
312 t->number_of_memory_devices = meminfo->dimm_cnt;
313
314 *current += len;
315 *handle += 1;
316 return len;
317}
318#endif
319
Subrata Banik7609c652017-05-19 14:50:09 +0530320void enable_power_aware_intr(void)
321{
322 uint8_t pair;
323
324 /* Enable Power Aware Interrupt Routing */
325 pair = MCHBAR8(MCH_PAIR);
326 pair &= ~0x7; /* Clear 2:0 */
327 pair |= 0x4; /* Fixed Priority */
328 MCHBAR8(MCH_PAIR) = pair;
329}
330
331static struct device_operations systemagent_ops = {
Elyes HAOUAS1d191272018-11-27 12:23:48 +0100332 .read_resources = systemagent_read_resources,
333 .set_resources = pci_dev_set_resources,
334 .enable_resources = pci_dev_enable_resources,
Subrata Banik7609c652017-05-19 14:50:09 +0530335 .init = soc_systemagent_init,
Subrata Banik6bbc91a2017-12-07 14:55:51 +0530336 .ops_pci = &pci_dev_ops_pci,
Julius Wernercd49cce2019-03-05 16:53:33 -0800337#if CONFIG(HAVE_ACPI_TABLES)
Werner Zehd12530c2018-12-14 13:09:12 +0100338 .write_acpi_tables = sa_write_acpi_tables,
339#endif
Lijian Zhao357e5522019-04-11 13:07:00 -0700340#if CONFIG(GENERATE_SMBIOS_TABLES)
341 .get_smbios_data = sa_smbios_write_type_16,
342#endif
Subrata Banik7609c652017-05-19 14:50:09 +0530343};
344
345static const unsigned short systemagent_ids[] = {
346 PCI_DEVICE_ID_INTEL_GLK_NB,
347 PCI_DEVICE_ID_INTEL_APL_NB,
Lijian Zhaobbedef92017-07-29 16:38:38 -0700348 PCI_DEVICE_ID_INTEL_CNL_ID_U,
349 PCI_DEVICE_ID_INTEL_CNL_ID_Y,
Subrata Banik7609c652017-05-19 14:50:09 +0530350 PCI_DEVICE_ID_INTEL_SKL_ID_U,
351 PCI_DEVICE_ID_INTEL_SKL_ID_Y,
352 PCI_DEVICE_ID_INTEL_SKL_ID_ULX,
Maxim Polyakovdde937c2019-09-09 15:50:03 +0300353 PCI_DEVICE_ID_INTEL_SKL_ID_H_4,
Keno Fischer1044eba2019-06-07 01:55:56 -0400354 PCI_DEVICE_ID_INTEL_SKL_ID_H_2,
355 PCI_DEVICE_ID_INTEL_SKL_ID_S_2,
356 PCI_DEVICE_ID_INTEL_SKL_ID_S_4,
Lean Sheng Tan38c3ff72019-05-27 13:06:35 +0800357 PCI_DEVICE_ID_INTEL_WHL_ID_W_2,
358 PCI_DEVICE_ID_INTEL_WHL_ID_W_4,
Gaggery Tsaie415a4c2018-03-21 22:36:18 +0800359 PCI_DEVICE_ID_INTEL_KBL_ID_S,
Subrata Banik7609c652017-05-19 14:50:09 +0530360 PCI_DEVICE_ID_INTEL_SKL_ID_H_EM,
361 PCI_DEVICE_ID_INTEL_KBL_ID_U,
362 PCI_DEVICE_ID_INTEL_KBL_ID_Y,
363 PCI_DEVICE_ID_INTEL_KBL_ID_H,
364 PCI_DEVICE_ID_INTEL_KBL_U_R,
V Sowmyaacc2a482018-01-23 15:27:23 +0530365 PCI_DEVICE_ID_INTEL_KBL_ID_DT,
Christian Walter3d840382019-05-17 19:37:16 +0200366 PCI_DEVICE_ID_INTEL_KBL_ID_DT_2,
Maulikfc19ab52018-01-05 22:40:35 +0530367 PCI_DEVICE_ID_INTEL_CFL_ID_U,
Christian Walterccac15a2019-08-13 09:55:37 +0200368 PCI_DEVICE_ID_INTEL_CFL_ID_U_2,
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +0800369 PCI_DEVICE_ID_INTEL_CFL_ID_H,
Christian Walterccac15a2019-08-13 09:55:37 +0200370 PCI_DEVICE_ID_INTEL_CFL_ID_H_4,
Lean Sheng Tan38c3ff72019-05-27 13:06:35 +0800371 PCI_DEVICE_ID_INTEL_CFL_ID_H_8,
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +0800372 PCI_DEVICE_ID_INTEL_CFL_ID_S,
Christian Walterccac15a2019-08-13 09:55:37 +0200373 PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2,
Felix Singerd298ffe2019-07-28 13:27:11 +0200374 PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4,
Lean Sheng Tan38c3ff72019-05-27 13:06:35 +0800375 PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8,
Christian Walterccac15a2019-08-13 09:55:37 +0200376 PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4,
377 PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6,
Lean Sheng Tan38c3ff72019-05-27 13:06:35 +0800378 PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8,
Christian Walterccac15a2019-08-13 09:55:37 +0200379 PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4,
380 PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6,
381 PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8,
Aamir Bohra9eac0392018-06-30 12:07:04 +0530382 PCI_DEVICE_ID_INTEL_ICL_ID_U,
383 PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2,
384 PCI_DEVICE_ID_INTEL_ICL_ID_Y,
385 PCI_DEVICE_ID_INTEL_ICL_ID_Y_2,
Ronak Kanabarf606a2f2019-02-04 16:06:50 +0530386 PCI_DEVICE_ID_INTEL_CML_ULT,
Subrata Banikba8af582019-02-27 15:00:55 +0530387 PCI_DEVICE_ID_INTEL_CML_ULT_2_2,
Ronak Kanabarf606a2f2019-02-04 16:06:50 +0530388 PCI_DEVICE_ID_INTEL_CML_ULT_6_2,
389 PCI_DEVICE_ID_INTEL_CML_ULX,
390 PCI_DEVICE_ID_INTEL_CML_S,
Gaggery Tsaifdcc9ab2019-11-04 20:49:10 -0800391 PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2,
392 PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2,
393 PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2,
Ronak Kanabarf606a2f2019-02-04 16:06:50 +0530394 PCI_DEVICE_ID_INTEL_CML_H,
Jamie Chen6bb9aaf2019-12-20 19:30:33 +0800395 PCI_DEVICE_ID_INTEL_CML_H_4_2,
Ronak Kanabarf606a2f2019-02-04 16:06:50 +0530396 PCI_DEVICE_ID_INTEL_CML_H_8_2,
Ravi Sarawadi6b5bf402019-10-21 22:25:04 -0700397 PCI_DEVICE_ID_INTEL_TGL_ID_U,
Subrata Banikae695752019-11-12 12:47:43 +0530398 PCI_DEVICE_ID_INTEL_TGL_ID_U_1,
Ravi Sarawadi6b5bf402019-10-21 22:25:04 -0700399 PCI_DEVICE_ID_INTEL_TGL_ID_Y,
rkanabar263f1292019-11-28 10:41:45 +0530400 PCI_DEVICE_ID_INTEL_JSL_PRE_PROD,
Subrata Banik7609c652017-05-19 14:50:09 +0530401 0
402};
403
404static const struct pci_driver systemagent_driver __pci_driver = {
405 .ops = &systemagent_ops,
406 .vendor = PCI_VENDOR_ID_INTEL,
407 .devices = systemagent_ids
408};