blob: ec5ee910d9d0d6a586d7a31c2a01ac134fcd350f [file] [log] [blame]
Marc Jones24484842017-05-04 21:17:45 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
Martin Roth48e44ee2017-11-12 14:54:09 -07005 * Copyright (C) 2017 Google, Inc.
Marc Jones24484842017-05-04 21:17:45 -06006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
Marc Jones24484842017-05-04 21:17:45 -060017#include <arch/io.h>
18#include <reset.h>
Martin Roth48e44ee2017-11-12 14:54:09 -070019#include <soc/northbridge.h>
20#include <soc/pci_devs.h>
Patrick Rudolphe56189c2018-04-18 10:11:59 +020021#include <device/pci_ops.h>
Marc Jonesdfeb1c42017-08-07 19:08:24 -060022#include <soc/southbridge.h>
Marshall Dawson69486ca2019-05-02 12:03:45 -060023#include <amdblocks/acpimmio.h>
Nico Huber73c11192018-10-06 18:20:47 +020024#include <amdblocks/reset.h>
Marc Jones24484842017-05-04 21:17:45 -060025
Marshall Dawson2e49cf122018-08-03 17:05:22 -060026void set_warm_reset_flag(void)
27{
28 u32 htic;
29 htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
30 htic |= HTIC_COLD_RST_DET;
31 pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
32}
33
34int is_warm_reset(void)
35{
36 u32 htic;
37 htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
38 return !!(htic & HTIC_COLD_RST_DET);
39}
40
Martin Roth48e44ee2017-11-12 14:54:09 -070041/* Clear bits 5, 9 & 10, used to signal the reset type */
42static void clear_bios_reset(void)
Marc Jones24484842017-05-04 21:17:45 -060043{
44 u32 htic;
Martin Roth48e44ee2017-11-12 14:54:09 -070045 htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
46 htic &= ~HTIC_BIOSR_DETECT;
47 pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
Marc Jones24484842017-05-04 21:17:45 -060048}
49
Nico Huber73c11192018-10-06 18:20:47 +020050void do_cold_reset(void)
Marc Jones24484842017-05-04 21:17:45 -060051{
Martin Roth48e44ee2017-11-12 14:54:09 -070052 clear_bios_reset();
53
54 /* De-assert and then assert all PwrGood signals on CF9 reset. */
55 pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
56 TOGGLE_ALL_PWR_GOOD);
57 outb(RST_CMD | SYS_RST, SYS_RESET);
58}
59
Nico Huber73c11192018-10-06 18:20:47 +020060void do_warm_reset(void)
Martin Roth48e44ee2017-11-12 14:54:09 -070061{
Marshall Dawson2e49cf122018-08-03 17:05:22 -060062 set_warm_reset_flag();
Martin Roth48e44ee2017-11-12 14:54:09 -070063 clear_bios_reset();
64
65 /* Assert reset signals only. */
66 outb(RST_CMD | SYS_RST, SYS_RESET);
Marc Jones24484842017-05-04 21:17:45 -060067}
Nico Huber73c11192018-10-06 18:20:47 +020068
69void do_board_reset(void)
70{
71 /* TODO: Would a warm_reset() suffice? */
72 do_cold_reset();
73}