| Uwe Hermann | 0675d5c | 2010-11-14 20:10:11 +0000 | [diff] [blame^] | 1 | chip northbridge/amd/amdk8/root_complex # Root complex |
| 2 | device lapic_cluster 0 on # (L)APIC cluster |
| 3 | chip cpu/amd/socket_F # CPU socket |
| 4 | device lapic 0 on end # Local APIC of the CPU |
| 5 | end |
| 6 | end |
| 7 | device pci_domain 0 on # PCI domain |
| 8 | chip northbridge/amd/amdk8 # Northbridge / RAM controller |
| 9 | device pci 18.0 on # Link 0 == LDT 0 |
| 10 | chip southbridge/nvidia/mcp55 # Southbridge |
| 11 | device pci 0.0 on end # HT |
| 12 | device pci 1.0 on # LPC |
| 13 | chip superio/winbond/w83627ehg # Super I/O |
| 14 | device pnp 2e.0 off # Floppy |
| 15 | io 0x60 = 0x3f0 |
| 16 | irq 0x70 = 6 |
| 17 | drq 0x74 = 2 |
| 18 | end |
| 19 | device pnp 2e.1 off # Parallel port |
| 20 | io 0x60 = 0x378 |
| 21 | irq 0x70 = 7 |
| 22 | end |
| 23 | device pnp 2e.2 on # Com1 |
| 24 | io 0x60 = 0x3f8 |
| 25 | irq 0x70 = 4 |
| 26 | end |
| 27 | device pnp 2e.3 off # Com2 |
| 28 | io 0x60 = 0x2f8 |
| 29 | irq 0x70 = 3 |
| 30 | end |
| 31 | device pnp 2e.5 on # PS/2 keyboard |
| 32 | io 0x60 = 0x60 |
| 33 | io 0x62 = 0x64 |
| 34 | irq 0x70 = 1 |
| 35 | irq 0x72 = 12 |
| 36 | end |
| 37 | device pnp 2e.6 off # SFI |
| 38 | io 0x62 = 0x100 |
| 39 | end |
| 40 | device pnp 2e.7 off # GPIO, Game port, MIDI |
| 41 | io 0x60 = 0x220 |
| 42 | io 0x62 = 0x300 |
| 43 | irq 0x70 = 9 |
| 44 | end |
| 45 | device pnp 2e.8 off end # WDTO PLED |
| 46 | device pnp 2e.9 off end # GPIO SUSLED |
| 47 | device pnp 2e.a off end # ACPI |
| 48 | device pnp 2e.b on # Hardware monitor |
| 49 | io 0x60 = 0x290 |
| 50 | irq 0x70 = 5 |
| 51 | end |
| 52 | end |
| 53 | end |
| 54 | device pci 1.1 on # SM 0 |
| 55 | chip drivers/generic/generic # DIMM 0-0-0 |
| 56 | device i2c 50 on end |
| 57 | end |
| 58 | chip drivers/generic/generic # DIMM 0-0-1 |
| 59 | device i2c 51 on end |
| 60 | end |
| 61 | chip drivers/generic/generic # DIMM 0-1-0 |
| 62 | device i2c 52 on end |
| 63 | end |
| 64 | chip drivers/generic/generic # DIMM 0-1-1 |
| 65 | device i2c 53 on end |
| 66 | end |
| 67 | chip drivers/generic/generic # DIMM 1-0-0 |
| 68 | device i2c 54 on end |
| 69 | end |
| 70 | chip drivers/generic/generic # DIMM 1-0-1 |
| 71 | device i2c 55 on end |
| 72 | end |
| 73 | chip drivers/generic/generic # DIMM 1-1-0 |
| 74 | device i2c 56 on end |
| 75 | end |
| 76 | chip drivers/generic/generic # DIMM 1-1-1 |
| 77 | device i2c 57 on end |
| 78 | end |
| 79 | end |
| 80 | device pci 1.1 on # SM 1 |
| 81 | # PCI device SMBus address will |
| 82 | # depend on addon PCI device, do |
| 83 | # we need to scan_smbus_bus? |
| 84 | # chip drivers/generic/generic # PCIXA slot 1 |
| 85 | # device i2c 50 on end |
| 86 | # end |
| 87 | # chip drivers/generic/generic # PCIXB slot 1 |
| 88 | # device i2c 51 on end |
| 89 | # end |
| 90 | # chip drivers/generic/generic # PCIXB slot 2 |
| 91 | # device i2c 52 on end |
| 92 | # end |
| 93 | # chip drivers/generic/generic # PCI slot 1 |
| 94 | # device i2c 53 on end |
| 95 | # end |
| 96 | # chip drivers/generic/generic # Master MCP55 PCI-E |
| 97 | # device i2c 54 on end |
| 98 | # end |
| 99 | # chip drivers/generic/generic # Slave MCP55 PCI-E |
| 100 | # device i2c 55 on end |
| 101 | # end |
| 102 | chip drivers/generic/generic # MAC EEPROM |
| 103 | device i2c 51 on end |
| 104 | end |
| 105 | end |
| 106 | device pci 2.0 on end # USB 1.1 |
| 107 | device pci 2.1 on end # USB 2 |
| 108 | device pci 4.0 on end # IDE |
| 109 | device pci 5.0 on end # SATA 0 |
| 110 | device pci 5.1 on end # SATA 1 |
| 111 | device pci 5.2 on end # SATA 2 |
| 112 | device pci 6.0 on end # PCI |
| 113 | device pci 6.1 on end # AZA |
| 114 | device pci 8.0 on end # NIC |
| 115 | device pci 9.0 on end # NIC |
| 116 | device pci a.0 on end # PCI E 5 |
| 117 | device pci b.0 off end # PCI E 4 |
| 118 | device pci c.0 off end # PCI E 3 |
| 119 | device pci d.0 on end # PCI E 2 |
| 120 | device pci e.0 off end # PCI E 1 |
| 121 | device pci f.0 on end # PCI E 0 |
| 122 | register "ide0_enable" = "1" |
| 123 | register "sata0_enable" = "1" |
| 124 | register "sata1_enable" = "1" |
| 125 | # 1: SMBus under 2e.8, 2: SM0 3: SM1 |
| 126 | register "mac_eeprom_smbus" = "3" |
| 127 | register "mac_eeprom_addr" = "0x51" |
| 128 | end |
| 129 | end |
| 130 | device pci 18.0 on end # Link 1 |
| 131 | device pci 18.0 on # Link 2 == LDT 2 |
| 132 | chip southbridge/nvidia/mcp55 # Southbridge |
| 133 | device pci 0.0 on end # HT |
| 134 | device pci 1.0 on end # LPC |
| 135 | device pci 1.1 on end # SM 0 |
| 136 | device pci 2.0 off end # USB 1.1 |
| 137 | device pci 2.1 off end # USB 2 |
| 138 | device pci 4.0 off end # IDE |
| 139 | device pci 5.0 on end # SATA 0 |
| 140 | device pci 5.1 on end # SATA 1 |
| 141 | device pci 5.2 on end # SATA 2 |
| 142 | device pci 6.0 off end # PCI |
| 143 | device pci 6.1 off end # AZA |
| 144 | device pci 8.0 on end # NIC |
| 145 | device pci 9.0 on end # NIC |
| 146 | device pci a.0 on end # PCI E 5 |
| 147 | device pci b.0 off end # PCI E 4 |
| 148 | device pci c.0 off end # PCI E 3 |
| 149 | device pci d.0 on end # PCI E 2 |
| 150 | device pci e.0 on end # PCI E 1 |
| 151 | device pci f.0 on end # PCI E 0 |
| 152 | register "ide0_enable" = "1" |
| 153 | register "sata0_enable" = "1" |
| 154 | register "sata1_enable" = "1" |
| 155 | # 1: SMBus under 2e.8, 2: SM0 3: SM1 |
| 156 | register "mac_eeprom_smbus" = "3" |
| 157 | register "mac_eeprom_addr" = "0x51" |
| 158 | end |
| 159 | end |
| 160 | device pci 18.1 on end |
| 161 | device pci 18.2 on end |
| 162 | device pci 18.3 on end |
| 163 | end |
| 164 | end |
| 165 | # chip drivers/generic/debug |
| 166 | # device pnp 0.0 off end # chip name |
| 167 | # device pnp 0.1 on end # pci_regs_all |
| 168 | # device pnp 0.2 on end # mem |
| 169 | # device pnp 0.3 off end # cpuid |
| 170 | # device pnp 0.4 on end # smbus_regs_all |
| 171 | # device pnp 0.5 off end # dual core msr |
| 172 | # device pnp 0.6 off end # cache size |
| 173 | # device pnp 0.7 off end # tsc |
| 174 | # device pnp 0.8 off end # io |
| 175 | # device pnp 0.9 off end # io |
| 176 | # end |
| 177 | end |