Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <baytrail/pci_devs.h> |
| 24 | #include <baytrail/ramstage.h> |
| 25 | #include <drivers/intel/fsp/fsp_util.h> |
| 26 | #include "chip.h" |
| 27 | |
| 28 | static void pci_domain_set_resources(device_t dev) |
| 29 | { |
| 30 | assign_resources(dev->link_list); |
| 31 | } |
| 32 | |
| 33 | static void finalize_dev (device_t dev) |
| 34 | { |
| 35 | /* |
| 36 | * Notify FSP for PostPciEnumeration. |
| 37 | * Northbridge APIC init should be early and late enough... |
| 38 | */ |
| 39 | printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); |
| 40 | FspNotify(EnumInitPhaseAfterPciEnumeration); |
| 41 | } |
| 42 | |
| 43 | static struct device_operations pci_domain_ops = { |
| 44 | .read_resources = pci_domain_read_resources, |
| 45 | .set_resources = pci_domain_set_resources, |
| 46 | .enable_resources = NULL, |
| 47 | .init = NULL, |
| 48 | .final = &finalize_dev, |
| 49 | .scan_bus = pci_domain_scan_bus, |
| 50 | .ops_pci_bus = pci_bus_default_ops, |
| 51 | }; |
| 52 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 53 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 0625a8b | 2014-10-31 08:03:16 +1100 | [diff] [blame^] | 54 | .read_resources = DEVICE_NOOP, |
| 55 | .set_resources = DEVICE_NOOP, |
| 56 | .enable_resources = DEVICE_NOOP, |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 57 | .init = baytrail_init_cpus, |
| 58 | .scan_bus = NULL, |
| 59 | }; |
| 60 | |
| 61 | static void enable_dev(device_t dev) |
| 62 | { |
| 63 | printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", |
| 64 | dev_name(dev), dev->path.type); |
| 65 | |
| 66 | /* Set the operations if it is a special bus type */ |
| 67 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 68 | dev->ops = &pci_domain_ops; |
| 69 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 70 | dev->ops = &cpu_bus_ops; |
| 71 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 72 | /* Handle south cluster enablement. */ |
| 73 | if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && |
| 74 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 75 | southcluster_enable_dev(dev); |
| 76 | } |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | static void finalize_chip(void *chip_info) |
| 81 | { |
| 82 | /* Notify FSP for ReadyToBoot */ |
| 83 | printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); |
| 84 | FspNotify(EnumInitPhaseReadyToBoot); |
| 85 | |
| 86 | } |
| 87 | |
| 88 | /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ |
| 89 | static void soc_init(void *chip_info) |
| 90 | { |
| 91 | baytrail_init_pre_device(); |
| 92 | } |
| 93 | |
| 94 | struct chip_operations soc_intel_fsp_baytrail_ops = { |
| 95 | CHIP_NAME("Intel BayTrail SoC") |
| 96 | .enable_dev = enable_dev, |
| 97 | .init = soc_init, |
| 98 | .final = &finalize_chip, |
| 99 | }; |
| 100 | |
| 101 | static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 102 | { |
| 103 | if (!vendor || !device) { |
| 104 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 105 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 106 | } else { |
| 107 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 108 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | struct pci_operations soc_pci_ops = { |
| 113 | .set_subsystem = &pci_set_subsystem, |
| 114 | }; |