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Martin Roth5c354b92019-04-22 14:55:16 -06001##
2## This file is part of the coreboot project.
3##
Marshall Dawson62611412019-06-19 11:46:06 -06004## Copyright (C) 2019 Advanced Micro Devices, Inc.
Martin Roth5c354b92019-04-22 14:55:16 -06005##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15
Martin Roth1f337622019-04-22 16:08:31 -060016config SOC_AMD_PICASSO
Martin Roth5c354b92019-04-22 14:55:16 -060017 bool
18 help
Martin Roth1f337622019-04-22 16:08:31 -060019 AMD Picasso support
Martin Roth5c354b92019-04-22 14:55:16 -060020
Martin Roth1f337622019-04-22 16:08:31 -060021if SOC_AMD_PICASSO
Martin Roth5c354b92019-04-22 14:55:16 -060022
23config CPU_SPECIFIC_OPTIONS
24 def_bool y
25 select ARCH_BOOTBLOCK_X86_32
26 select ARCH_VERSTAGE_X86_32
27 select ARCH_ROMSTAGE_X86_32
28 select ARCH_RAMSTAGE_X86_32
29 select X86_AMD_FIXED_MTRRS
Marshall Dawson34c30562019-07-16 15:18:00 -060030 select X86_AMD_INIT_SIPI
Martin Roth5c354b92019-04-22 14:55:16 -060031 select ACPI_AMD_HARDWARE_SLEEP_VALUES
Martin Roth5c354b92019-04-22 14:55:16 -060032 select DRIVERS_I2C_DESIGNWARE
33 select GENERIC_GPIO_LIB
Martin Roth5c354b92019-04-22 14:55:16 -060034 select IOAPIC
35 select HAVE_USBDEBUG_OPTIONS
Marshall Dawson80d0b012019-06-19 12:29:23 -060036 select TSC_CONSTANT_RATE
37 select TSC_MONOTONIC_TIMER
Richard Spiegel65562cd2019-08-21 10:27:05 -070038 select SOC_AMD_COMMON_BLOCK_SPI
Martin Roth5c354b92019-04-22 14:55:16 -060039 select TSC_SYNC_LFENCE
Marshall Dawson80d0b012019-06-19 12:29:23 -060040 select UDELAY_TSC
Martin Roth5c354b92019-04-22 14:55:16 -060041 select COLLECT_TIMESTAMPS
42 select SOC_AMD_PI
43 select SOC_AMD_COMMON
44 select SOC_AMD_COMMON_BLOCK
45 select SOC_AMD_COMMON_BLOCK_IOMMU
46 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
47 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
48 select SOC_AMD_COMMON_BLOCK_ACPI
49 select SOC_AMD_COMMON_BLOCK_LPC
50 select SOC_AMD_COMMON_BLOCK_PCI
51 select SOC_AMD_COMMON_BLOCK_HDA
52 select SOC_AMD_COMMON_BLOCK_SATA
Martin Roth5c354b92019-04-22 14:55:16 -060053 select SOC_AMD_COMMON_BLOCK_S3
54 select C_ENVIRONMENT_BOOTBLOCK
55 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
56 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
Martin Roth5c354b92019-04-22 14:55:16 -060057 select PARALLEL_MP
58 select PARALLEL_MP_AP_WORK
59 select HAVE_SMI_HANDLER
Martin Roth5c354b92019-04-22 14:55:16 -060060 select SSE2
61 select RTC
Martin Roth5c354b92019-04-22 14:55:16 -060062
63config VBOOT
64 select VBOOT_SEPARATE_VERSTAGE
65 select VBOOT_STARTS_IN_BOOTBLOCK
66 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
67 select VBOOT_VBNV_CMOS
68 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
69
Kyösti Mälkki9c55ee32019-07-22 09:34:50 +030070config HAVE_BOOTBLOCK
71 bool
72 default n
73
Martin Roth5c354b92019-04-22 14:55:16 -060074# TODO: Sync these with definitions in PI vendorcode.
75# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
76# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
77
78config DCACHE_RAM_BASE
79 hex
80 default 0x30000
81
82config DCACHE_RAM_SIZE
83 hex
84 default 0x10000
85
86config DCACHE_BSP_STACK_SIZE
87 depends on C_ENVIRONMENT_BOOTBLOCK
88 hex
89 default 0x4000
90 help
91 The amount of anticipated stack usage in CAR by bootblock and
92 other stages.
93
94config PRERAM_CBMEM_CONSOLE_SIZE
95 hex
96 default 0x1600
97 help
98 Increase this value if preram cbmem console is getting truncated
99
100config CPU_ADDR_BITS
101 int
102 default 48
103
Martin Roth5c354b92019-04-22 14:55:16 -0600104config MMCONF_BASE_ADDRESS
105 hex
106 default 0xF8000000
107
108config MMCONF_BUS_NUMBER
109 int
110 default 64
111
112config VGA_BIOS_ID
113 string
Marshall Dawson0d441da2019-07-09 18:19:05 -0500114 default "1002,15d8"
Martin Roth5c354b92019-04-22 14:55:16 -0600115 help
116 The default VGA BIOS PCI vendor/device ID should be set to the
117 result of the map_oprom_vendev() function in northbridge.c.
118
119config VGA_BIOS_FILE
120 string
Marshall Dawson0d441da2019-07-09 18:19:05 -0500121 default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin"
Martin Roth5c354b92019-04-22 14:55:16 -0600122
123config S3_VGA_ROM_RUN
124 bool
125 default n
126
127config HEAP_SIZE
128 hex
129 default 0xc0000
130
131config EHCI_BAR
132 hex
133 default 0xfef00000
134
Martin Roth5c354b92019-04-22 14:55:16 -0600135config AMD_PUBKEY_FILE
136 string "AMD public Key"
Marshall Dawson62611412019-06-19 11:46:06 -0600137 default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin"
Martin Roth5c354b92019-04-22 14:55:16 -0600138
Martin Roth5c354b92019-04-22 14:55:16 -0600139config SERIRQ_CONTINUOUS_MODE
140 bool
141 default n
142 help
143 Set this option to y for serial IRQ in continuous mode.
144 Otherwise it is in quiet mode.
145
Marshall Dawsonbc4c9032019-06-11 12:18:20 -0600146config PICASSO_ACPI_IO_BASE
Martin Roth5c354b92019-04-22 14:55:16 -0600147 hex
148 default 0x400
149 help
150 Base address for the ACPI registers.
Martin Roth5c354b92019-04-22 14:55:16 -0600151
Marshall Dawsonbc4c9032019-06-11 12:18:20 -0600152config PICASSO_UART
153 bool "UART controller on Picasso"
Martin Roth5c354b92019-04-22 14:55:16 -0600154 default n
155 select DRIVERS_UART_8250MEM
156 select DRIVERS_UART_8250MEM_32
157 select NO_UART_ON_SUPERIO
158 select UART_OVERRIDE_REFCLK
159 help
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600160 There are four memory-mapped UARTs controllers in Picasso at:
161 0: 0xfedc9000
162 1: 0xfedca000
163 2: 0xfedc3000
164 3: 0xfedcf000
165
166choice PICASSO_UART_CLOCK_SOURCE
167 prompt "UART Frequency"
168 depends on PICASSO_UART
169 default PICASSO_UART_48MZ
170
171config PICASSO_UART_48MZ
172 bool "48 MHz clock"
173 help
174 Select this option for the most compatibility.
175
176config PICASSO_UART_1_8MZ
177 bool "1.8432 MHz clock"
178 help
179 Select this option if an old payload or Linux ttyS0 arguments
180 require it.
181
182endchoice
183
184config PICASSO_UART_LEGACY
185 bool "Decode legacy I/O range"
186 depends on PICASSO_UART
187 help
188 Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may
189 decode legacy addresses and this option enables the one used for the
190 console. A UART accessed with I/O does not allow all the features
191 of MMIO. The MMIO decode is still present when this option is used.
Martin Roth5c354b92019-04-22 14:55:16 -0600192
193config CONSOLE_UART_BASE_ADDRESS
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600194 depends on CONSOLE_SERIAL && PICASSO_UART
Martin Roth5c354b92019-04-22 14:55:16 -0600195 hex
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600196 default 0xfedc9000 if UART_FOR_CONSOLE = 0
197 default 0xfedca000 if UART_FOR_CONSOLE = 1
198 default 0xfedc3000 if UART_FOR_CONSOLE = 2
199 default 0xfedcf000 if UART_FOR_CONSOLE = 3
Martin Roth5c354b92019-04-22 14:55:16 -0600200
201config SMM_TSEG_SIZE
202 hex
203 default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
204 default 0x0
205
206config SMM_RESERVED_SIZE
207 hex
208 default 0x150000
209
210config SMM_MODULE_STACK_SIZE
211 hex
212 default 0x800
213
214config ACPI_CPU_STRING
215 string
216 default "\\_PR.P%03d"
217
218config ACPI_BERT
219 bool "Build ACPI BERT Table"
220 default y
221 depends on HAVE_ACPI_TABLES
222 help
223 Report Machine Check errors identified in POST to the OS in an
224 ACPI Boot Error Record Table. This option reserves an 8MB region
225 for building the error structures.
226
Marshall Dawson62611412019-06-19 11:46:06 -0600227config RO_REGION_ONLY
228 string
229 depends on CHROMEOS
230 default "apu/amdfw"
Martin Roth5c354b92019-04-22 14:55:16 -0600231
Marshall Dawson62611412019-06-19 11:46:06 -0600232config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
233 int
234 default 133
235
Marshall Dawson39a4ac12019-06-20 16:28:33 -0600236config PICASSO_LPC_IOMUX
237 bool
238 help
239 Picasso's LPC bus signals are MUXed with some of the EMMC signals.
240 Select this option if LPC signals are required.
241
Marshall Dawson62611412019-06-19 11:46:06 -0600242config MAINBOARD_POWER_RESTORE
243 def_bool n
244 help
245 This option determines what state to go to once power is restored
246 after having been lost in S0. Select this option to automatically
247 return to S0. Otherwise the system will remain in S5 once power
248 is restored.
249
250menu "PSP Configuration Options"
Martin Roth5c354b92019-04-22 14:55:16 -0600251
Martin Roth5c354b92019-04-22 14:55:16 -0600252config AMDFW_OUTSIDE_CBFS
253 bool "The AMD firmware is outside CBFS"
254 default n
255 help
256 The AMDFW (PSP) is typically locatable in cbfs. Select this
257 option to manually attach the generated amdfw.rom outside of
258 cbfs. The location is selected by the FWM position.
259
260config AMD_FWM_POSITION_INDEX
261 int "Firmware Directory Table location (0 to 5)"
262 range 0 5
263 default 0 if BOARD_ROMSIZE_KB_512
264 default 1 if BOARD_ROMSIZE_KB_1024
265 default 2 if BOARD_ROMSIZE_KB_2048
266 default 3 if BOARD_ROMSIZE_KB_4096
267 default 4 if BOARD_ROMSIZE_KB_8192
268 default 5 if BOARD_ROMSIZE_KB_16384
269 help
270 Typically this is calculated by the ROM size, but there may
271 be situations where you want to put the firmware directory
272 table in a different location.
273 0: 512 KB - 0xFFFA0000
274 1: 1 MB - 0xFFF20000
275 2: 2 MB - 0xFFE20000
276 3: 4 MB - 0xFFC20000
277 4: 8 MB - 0xFF820000
278 5: 16 MB - 0xFF020000
279
280comment "AMD Firmware Directory Table set to location for 512KB ROM"
281 depends on AMD_FWM_POSITION_INDEX = 0
282comment "AMD Firmware Directory Table set to location for 1MB ROM"
283 depends on AMD_FWM_POSITION_INDEX = 1
284comment "AMD Firmware Directory Table set to location for 2MB ROM"
285 depends on AMD_FWM_POSITION_INDEX = 2
286comment "AMD Firmware Directory Table set to location for 4MB ROM"
287 depends on AMD_FWM_POSITION_INDEX = 3
288comment "AMD Firmware Directory Table set to location for 8MB ROM"
289 depends on AMD_FWM_POSITION_INDEX = 4
290comment "AMD Firmware Directory Table set to location for 16MB ROM"
291 depends on AMD_FWM_POSITION_INDEX = 5
292
Marshall Dawson62611412019-06-19 11:46:06 -0600293config AMD_PUBKEY_FILE
294 string "AMD public Key"
295 default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin"
Martin Roth5c354b92019-04-22 14:55:16 -0600296
Marshall Dawson62611412019-06-19 11:46:06 -0600297config PSP_APCB_FILE
298 string "APCB file"
Martin Roth5c354b92019-04-22 14:55:16 -0600299 help
Marshall Dawson62611412019-06-19 11:46:06 -0600300 The name of the AGESA Parameter Customization Block.
301
302config PSP_APOB_DESTINATION
303 hex
304 default 0x9f00000
305 help
306 Location in DRAM where the PSP will copy the AGESA PSP Output
307 Block.
308
309config PSP_APOB_NV_ADDRESS
310 hex "Base address of APOB NV"
311 default 0xffa68000
312 help
313 Location in flash where the PSP can find the S3 restore information.
314 Place this on a boundary that the flash device can erase.
315 TODO: The above default value is arbitrary, but eventually coreboot's
316 MRC cache base address should be used.
317
318config PSP_APOB_NV_SIZE
319 hex "Size of APOB NV to be reserved"
320 default 0x10000
321 help
322 Size of the S3 restore information. Make this a multiple of the
323 size the flash device can erase.
324 TODO: The above default value is arbitrary, but eventually coreboot's
325 MRC cache size should be used.
326
327config USE_PSPSCUREOS
328 bool "Include PSP SecureOS blobs in PSP build"
329 default y
330 help
331 Include the PspSecureOs and PspTrustlet binaries in the PSP build.
332
333 If unsure, answer 'y'
334
335config PSP_LOAD_MP2_FW
336 bool "Include MP2 blobs in PSP build"
337 default y
338 help
339 Include the MP2 firmwares and configuration into the PSP build.
340
341 If unsure, answer 'y'
342
343config PSP_LOAD_S0I3_FW
344 bool "Include S0I3 blob in PSP build"
345 help
346 Select this item to include the S0i3 file into the PSP build.
347
348config HAVE_PSP_WHITELIST_FILE
349 bool "Include a debug whitelist file in PSP build"
350 default n
351 help
352 Support secured unlock prior to reset using a whitelisted
353 number? This feature requires a signed whitelist image and
354 bootloader from AMD.
355
356 If unsure, answer 'n'
357
358config PSP_WHITELIST_FILE
359 string "Debug whitelist file name"
360 depends on HAVE_PSP_WHITELIST_FILE
361 default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin"
362
363endmenu
Martin Roth5c354b92019-04-22 14:55:16 -0600364
Martin Roth1f337622019-04-22 16:08:31 -0600365endif # SOC_AMD_PICASSO