blob: 793cc1bfad6d5fd2463682a289ff77333bec4128 [file] [log] [blame]
Timothy Pearsonbfa19e12016-01-05 11:00:49 -06001/*
2 * This file is part of the coreboot project.
3 *
Timothy Pearsonbfa19e12016-01-05 11:00:49 -06004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <stdint.h>
15#include <cpu/x86/msr.h>
Elyes HAOUAS400ce552018-10-12 10:54:30 +020016#include <cpu/amd/msr.h>
Timothy Pearsonbfa19e12016-01-05 11:00:49 -060017#include <cpu/x86/tsc.h>
18
19unsigned long tsc_freq_mhz(void)
20{
21 msr_t msr;
22 uint8_t cpufid;
23 uint8_t cpudid;
24
25 /* On Family 10h/15h CPUs the TSC increments
Elyes HAOUAS2765a892016-09-01 19:44:56 +020026 * at the P0 clock rate. Read the P0 clock
27 * frequency from the P0 MSR and convert
28 * to MHz. See also the Family 15h BKDG
29 * Rev. 3.14 page 569.
30 */
Elyes HAOUAS400ce552018-10-12 10:54:30 +020031 msr = rdmsr(PSTATE_0_MSR);
Timothy Pearsonbfa19e12016-01-05 11:00:49 -060032 cpufid = (msr.lo & 0x3f);
33 cpudid = (msr.lo & 0x1c0) >> 6;
34
35 return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
36}