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Marc Jonesc74e3622008-04-22 23:09:34 +00001/*
2 * This file is part of the coreboot project.
3 *
Marc Jonesc74e3622008-04-22 23:09:34 +00004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
Marc Jonesc74e3622008-04-22 23:09:34 +000012 */
13
Patrick Georgi3d5bb232010-05-09 21:15:13 +000014#include <northbridge/amd/amdmct/amddefs.h>
15#include <cpu/amd/mtrr.h>
Elyes HAOUAS400ce552018-10-12 10:54:30 +020016#include <cpu/amd/msr.h>
Marc Jonesc74e3622008-04-22 23:09:34 +000017
18/*
19 * Default MSR and errata settings.
20 */
21static const struct {
22 u32 msr;
Timothy Pearson730a0432015-10-16 13:51:51 -050023 uint64_t revision;
Marc Jonesc74e3622008-04-22 23:09:34 +000024 u32 platform;
25 u32 data_lo;
26 u32 data_hi;
27 u32 mask_lo;
28 u32 mask_hi;
29} fam10_msr_default[] = {
Timothy Pearson730a0432015-10-16 13:51:51 -050030 { TOP_MEM2, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +000031 0x00000000, 0x00000000,
32 0xFFFFFFFF, 0xFFFFFFFF },
33
Elyes HAOUAS400ce552018-10-12 10:54:30 +020034 { SYSCFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +000035 3 << 21, 0x00000000,
36 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
37
Timothy Pearson730a0432015-10-16 13:51:51 -050038 { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL,
39 1 << 18, 0x00000000,
40 1 << 18, 0x00000000 }, /* Erratum 586: [DEIBP]=1 */
Marc Jonesc74e3622008-04-22 23:09:34 +000041
Timothy Pearson730a0432015-10-16 13:51:51 -050042 { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL,
43 1 << 15, 0x00000000,
44 1 << 15, 0x00000000 }, /* Erratum 593: [BSRP]=1 */
45
46 { MC1_CTL_MASK, AMD_OR_C0, AMD_PTYPE_ALL,
47 1 << 15, 0x00000000,
48 1 << 15, 0x00000000 }, /* Erratum 739: [BSRP]=1 */
49
50 { 0xc0011000, AMD_FAM15_ALL, AMD_PTYPE_ALL,
51 1 << 16, 0x00000000,
52 1 << 16, 0x00000000 }, /* Erratum 608: [bit 16]=1 */
53
54 { 0xc0011000, AMD_OR_C0, AMD_PTYPE_ALL,
55 1 << 15, 0x00000000,
56 1 << 15, 0x00000000 }, /* Erratum 727: [bit 15]=1 */
57
58 { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +000059 0xF << 19, 0x00000000,
60 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */
61
Timothy Pearson730a0432015-10-16 13:51:51 -050062 { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
63 1 << 10, 0x00000000,
64 1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */
65
Elyes HAOUAS400ce552018-10-12 10:54:30 +020066 { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_SVR,
Marc Jonesc74e3622008-04-22 23:09:34 +000067 0x00000000, 0x00000004,
Timothy Pearson730a0432015-10-16 13:51:51 -050068 0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */
Marc Jonesc74e3622008-04-22 23:09:34 +000069
Elyes HAOUAS400ce552018-10-12 10:54:30 +020070 { DC_CFG_MSR, AMD_DR_Bx, AMD_PTYPE_SVR,
Marc Jonesc74e3622008-04-22 23:09:34 +000071 0x00000000, 0x00000000,
Martin Roth4c3ab732013-07-08 16:23:54 -060072 0x00000000, 0x00000C00 }, /* Erratum 326 */
Marc Jonesc74e3622008-04-22 23:09:34 +000073
Elyes HAOUAS400ce552018-10-12 10:54:30 +020074 { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
Marc Jonesc74e3622008-04-22 23:09:34 +000075 0x00000000, 1 << 22,
76 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
77
Elyes HAOUAS400ce552018-10-12 10:54:30 +020078 { NB_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
Timothy Pearson730a0432015-10-16 13:51:51 -050079 1 << 23, 0x00000000,
80 1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */
81
Elyes HAOUAS400ce552018-10-12 10:54:30 +020082 { BU_CFG2_MSR, AMD_DR_Bx, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +000083 1 << 29, 0x00000000,
84 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
85
Elyes HAOUAS400ce552018-10-12 10:54:30 +020086 { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +000087 1 << 24, 0x00000000,
Marc Jones35b53612008-07-23 21:44:23 +000088 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
Marc Jonesc74e3622008-04-22 23:09:34 +000089
Elyes HAOUAS400ce552018-10-12 10:54:30 +020090 { LS_CFG_MSR, AMD_DR_GT_B0, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +000091 0 << 1, 0x00000000,
92 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
93
Elyes HAOUAS400ce552018-10-12 10:54:30 +020094 { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -050095 0x00000000, 1 << (39-32),
96 0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */
97
Elyes HAOUAS400ce552018-10-12 10:54:30 +020098 { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -050099 0xf << 1, 0x00000000,
100 0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */
101
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200102 { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000103 1 << 21, 0x00000000,
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200104 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000105
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200106 { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000107 1 << 23, 0x00000000,
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200108 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG_MSR[23]=1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000109
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200110 { BU_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500111 0 << 10, 0x00000000,
112 1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */
113
Marc Jonesc74e3622008-04-22 23:09:34 +0000114 /* CPUID_EXT_FEATURES */
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200115 { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
Marc Jonesc74e3622008-04-22 23:09:34 +0000116 1 << 28, 0x00000000,
117 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
118
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200119 { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC,
Marc Jonesc74e3622008-04-22 23:09:34 +0000120 0x00000000, 1 << (33-32),
121 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
Xavi Drudis Ferrane9f0dfe2010-08-22 19:49:46 +0000122
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200123 { DE_CFG_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500124 1 << 10, 0x00000000,
125 1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */
126
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200127 { BU_CFG2_MSR, AMD_DRBH_Cx, AMD_PTYPE_ALL,
Xavi Drudis Ferrane9f0dfe2010-08-22 19:49:46 +0000128 0x00000000, 1 << (35-32),
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700129 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
Zheng Bao2ca2f172011-03-28 04:29:14 +0000130
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200131 { BU_CFG3_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500132 0x00000000, 1 << (42-32),
133 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */
134
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200135 { BU_CFG3_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson68130f52015-08-09 02:47:51 -0500136 1 << 22, 0x00000000,
137 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */
Timothy Pearson730a0432015-10-16 13:51:51 -0500138
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200139 { EX_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500140 0x00000000, 1 << (54-32),
141 0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */
142
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200143 { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500144 1 << 23, 0x00000000,
145 1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */
146
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200147 { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500148 1 << 14, 0x00000000,
149 1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */
150
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200151 { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500152 1 << 12, 0x00000000,
153 1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */
154
Zheng Bao2ca2f172011-03-28 04:29:14 +0000155 { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
156 0x00000004, 0x00000000,
157 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */
158
159 { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
160 0x0000000C, 0x00000000,
161 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */
162
Timothy Pearson16a3a752015-09-03 17:43:52 -0500163 { OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL,
164 0x00000005, 0x00000000,
165 0x0000ffff, 0x00000000}, /* OSVW_ID_Length = 0x5 */
166
167 { OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL,
168 0x00000010, 0x00000000,
169 0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */
170
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200171 { BU_CFG2_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
Zheng Bao2ca2f172011-03-28 04:29:14 +0000172 0x00000000, 1 << (50-32),
173 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/
174
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200175 { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500176 0x00000000, 0x0 << (36-32),
177 0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */
178
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200179 { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500180 1 << 10, 0x00000000,
181 1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */
182
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200183 { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500184 1 << 11, 0x00000000,
185 1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */
186
Zheng Bao2ca2f172011-03-28 04:29:14 +0000187 { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
188 0x00000000, 1 << (51 - 32),
189 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
Timothy Pearson730a0432015-10-16 13:51:51 -0500190
191 { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
192 0x00000000, 1 << (56 - 32),
193 0x00000000, 1 << (56 - 32)}, /* [PerfCtrExtNB]=1 */
194
195 { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
196 0x00000000, 1 << (55 - 32),
197 0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */
198
Elyes HAOUAS400ce552018-10-12 10:54:30 +0200199 { IBS_OP_DATA3_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500200 0 << 16, 0x00000000,
201 1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */
202
203 { MC4_MISC0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
204 0x00000000, 0x1 << (52-32),
205 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
206
207 { MC4_MISC1, AMD_FAM15_ALL, AMD_PTYPE_ALL,
208 0x00000000, 0x1 << (52-32),
209 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
210
211 { MC4_MISC2, AMD_FAM15_ALL, AMD_PTYPE_ALL,
212 0x00000000, 0x1 << (52-32),
213 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000214};
215
216
217/*
218 * Default PCI and errata settings.
219 */
220static const struct {
221 u8 function;
222 u16 offset;
Timothy Pearson730a0432015-10-16 13:51:51 -0500223 uint64_t revision;
Marc Jonesc74e3622008-04-22 23:09:34 +0000224 u32 platform;
225 u32 data;
226 u32 mask;
227} fam10_pci_default[] = {
228
229 /* Function 0 - HT Config */
Timothy Pearson730a0432015-10-16 13:51:51 -0500230 { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
231 0x000e0000, 0x000e0000 }, /* [19:17] for 8bit APIC config */
Marc Jonesc74e3622008-04-22 23:09:34 +0000232
Timothy Pearson730a0432015-10-16 13:51:51 -0500233 { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
234 0x00400000, 0x00600000 }, /* [22:21] DsNpReqLmt = 10b */
235
236 { 0, 0x68, AMD_FAM10_LT_D, AMD_PTYPE_ALL,
237 0x00004000, 0x00006000 }, /* [14:13] BufRelPri = 2h */
238
239 { 0, 0x68, (AMD_FAM10_REV_D | AMD_FAM15_ALL), AMD_PTYPE_ALL,
240 0x00002000, 0x00006000 }, /* [14:13] BufRelPri = 1h */
241
242 { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
243 0x00000800, 0x00000800 }, /* [11] RspPassPW = 1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000244
245 /* Errata 281 Workaround */
246 { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
247 AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */
248
Timothy Pearson0122afb2015-07-30 14:07:15 -0500249 { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000250 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
251
Timothy Pearson0122afb2015-07-30 14:07:15 -0500252 { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000253 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
254
Timothy Pearson0122afb2015-07-30 14:07:15 -0500255 { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000256 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
257
Timothy Pearson0122afb2015-07-30 14:07:15 -0500258 { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000259 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
260
Marc Jonesaac8dc82009-06-17 15:33:57 +0000261 /* Link Global Retry Control Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500262 { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Timothy Pearson7c55f372015-08-02 21:36:24 -0500263 0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7,
264 HtRetryCrcDatInsDynEn = 0x1,
265 HtRetryCrcCmdPackDynEn = 0x1,
266 HtRetryCrcDatIns = 0x4,
267 HtRetryCrcCmdPack = 0x1,
268 ForceErrType = 0x0,
269 MultRetryErr = 0x0 */
Marc Jonesaac8dc82009-06-17 15:33:57 +0000270
Timothy Pearson21724932015-11-24 14:12:04 -0600271 /* Errata 600 */
272 { 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL,
273 0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */
274
Marc Jonesaac8dc82009-06-17 15:33:57 +0000275 /* Errata 351
276 * System software should program the Link Extended Control Registers[LS2En]
277 * (F0x[18C:170][8]) to 0b for all links. System software should also
278 * program Link Global Extended Control Register[ForceFullT0]
279 * (F0x16C[15:13]) to 000b */
280
Zheng Bao2ca2f172011-03-28 04:29:14 +0000281 { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
Marc Jonesaac8dc82009-06-17 15:33:57 +0000282 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000283 { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000284 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000285 { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000286 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000287 { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000288 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000289 { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000290 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000291 { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000292 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000293 { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000294 0x00000000, 0x00000100 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000295 { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000296 0x00000000, 0x00000100 },
Marc Jonesaac8dc82009-06-17 15:33:57 +0000297
Marc Jonesc74e3622008-04-22 23:09:34 +0000298 /* Link Global Extended Control Register */
Zheng Bao2ca2f172011-03-28 04:29:14 +0000299 { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
300 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
Timothy Pearson730a0432015-10-16 13:51:51 -0500301 * Set T0Time 14h per BKDG */
302
303 { 0, 0x170, AMD_FAM15_ALL, AMD_PTYPE_ALL,
304 0x00000100, 0x00000100 },
305 { 0, 0x174, AMD_FAM15_ALL, AMD_PTYPE_ALL,
306 0x00000100, 0x00000100 },
307 { 0, 0x178, AMD_FAM15_ALL, AMD_PTYPE_ALL,
308 0x00000100, 0x00000100 },
309 { 0, 0x17C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
310 0x00000100, 0x00000100 },
311 { 0, 0x180, AMD_FAM15_ALL, AMD_PTYPE_ALL,
312 0x00000100, 0x00000100 },
313 { 0, 0x184, AMD_FAM15_ALL, AMD_PTYPE_ALL,
314 0x00000100, 0x00000100 },
315 { 0, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL,
316 0x00000100, 0x00000100 },
317 { 0, 0x18C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
318 0x00000100, 0x00000100 },
319
320 /* Link Global Extended Control Register */
321 { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
322 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 111b,
323 * Set T0Time 26h per BKDG */
324
325 { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
326 0x7 << 13, 0x7 << 13 }, /* [15:13] ForceFullT0 = 7h */
327
328 { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
329 0x26, 0x3f }, /* [5:0] T0Time = 26h */
Marc Jonesaac8dc82009-06-17 15:33:57 +0000330
Marc Jonesc74e3622008-04-22 23:09:34 +0000331
332 /* Function 1 - Map Init */
333
334 /* Before reading F1x114_x2 or F1x114_x3 software must
335 * initialize the registers or NB Array MCA errors may
336 * occur. BIOS should initialize index 0h of F1x114_x2 and
337 * F1x114_x3 to prevent reads from F1x114 from generating NB
338 * Array MCA errors. BKDG Doc #3116 Rev 1.07
339 */
340
Marc Jones99fd2a32009-05-14 23:42:41 +0000341 { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000342 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
343
Marc Jones99fd2a32009-05-14 23:42:41 +0000344 { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000345 0x00000000, 0xFFFFFFFF }, /* Clear map */
346
Marc Jones99fd2a32009-05-14 23:42:41 +0000347 { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000348 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
349
Marc Jones99fd2a32009-05-14 23:42:41 +0000350 { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000351 0x00000000, 0xFFFFFFFF }, /* Clear map */
352
353 /* Function 2 - DRAM Controller */
354
355 /* Function 3 - Misc. Control */
Timothy Pearson730a0432015-10-16 13:51:51 -0500356 { 3, 0x40, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000357 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */
358
Timothy Pearson730a0432015-10-16 13:51:51 -0500359 { 3, 0x44, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jones35b53612008-07-23 21:44:23 +0000360 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1,
361 [27] NbMcaToMstCpuEn = 1,
362 [25] DisPciCfgCpuErrRsp = 1,
363 [21] SyncOnAnyErrEn = 1,
364 [20] SyncOnWDTEn = 1,
365 [6] CpuErrDis = 1,
366 [4] SyncPktPropDis = 1,
367 [3] SyncPktGenDis = 1,
368 [2] SyncOnUcEccEn = 1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000369
370 /* XBAR buffer settings */
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500371 { 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
372 0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0,
373 UpRspDBC = 0x1,
374 DatBuf24 = 0x1,
375 DnRspDBC = 0x1,
376 DnReqDBC = 0x1,
377 UpReqDBC = 0x2 */
378
379 /* XBAR buffer settings */
380 { 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL,
381 0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0,
382 UpRspDBC = 0x2,
383 DatBuf24 = 0x1,
384 DnRspDBC = 0x1,
385 DnReqDBC = 0x1,
386 UpReqDBC = 0x2 */
Timothy Pearson730a0432015-10-16 13:51:51 -0500387
388 /* XBAR buffer settings */
389 { 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500390 0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1,
391 UpRspDBC = 0x1,
392 DnRspDBC = 0x1,
393 DnReqDBC = 0x1,
394 UpReqDBC = 0x2 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000395
396 /* Errata 281 Workaround */
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500397 { 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1),
Marc Jonesc74e3622008-04-22 23:09:34 +0000398 AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
399
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500400 { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Marc Jonesc74e3622008-04-22 23:09:34 +0000401 0x60018051, 0x700780F7 },
402
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500403 { 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
404 0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0,
405 IsocPreqCBC = 0x0,
406 IsocReqCBC = 0x0,
407 UpRspCBC = 0x4,
408 DnPreqCBC = 0x1,
409 UpPreqCBC = 0x1,
410 DnRspCBC = 0x1,
411 DnReqCBC = 0x1,
412 UpReqCBC = 0x3 */
413
414 { 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL,
415 0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0,
416 IsocPreqCBC = 0x0,
417 IsocReqCBC = 0x0,
418 UpRspCBC = 0x5,
419 DnPreqCBC = 0x1,
420 UpPreqCBC = 0x1,
421 DnRspCBC = 0x1,
422 DnReqCBC = 0x1,
423 UpReqCBC = 0x3 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000424
Timothy Pearson730a0432015-10-16 13:51:51 -0500425 { 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500426 0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1,
427 IsocPreqCBC = 0x0,
428 IsocReqCBC = 0x1,
429 UpRspCBC = 0x7,
430 DnPreqCBC = 0x1,
431 UpPreqCBC = 0x1,
432 DnRspCBC = 0x1,
433 DnReqCBC = 0x1,
434 UpReqCBC = 0x5 */
Timothy Pearson730a0432015-10-16 13:51:51 -0500435
Marc Jones99fd2a32009-05-14 23:42:41 +0000436 { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500437 0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6,
438 IsocPreqCBC = 0x1,
439 IsocReqCBC = 0x2,
440 UpRspCBC = 0x2,
441 DnPreqCBC = 0x1,
442 UpPreqCBC = 0x1,
443 DnRspCBC = 0x1,
444 DnReqCBC = 0x1,
445 UpReqCBC = 0x1 */
446
447 { 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA,
448 0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
449 IsocPreqCBC = 0x0,
450 IsocReqCBC = 0x0,
451 ProbeCBC = 0x8,
452 DnPreqCBC = 0x1,
453 UpPreqCBC = 0x1,
454 DnReqCBC = 0x1,
455 UpReqCBC = 0x1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000456
Marc Jones99fd2a32009-05-14 23:42:41 +0000457 { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500458 0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0,
459 IsocPreqCBC = 0x0,
460 IsocReqCBC = 0x4,
461 ProbeCBC = 0x8,
462 DnPreqCBC = 0x0,
463 UpPreqCBC = 0x1,
464 DnReqCBC = 0x0,
465 UpReqCBC = 0x1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000466
Timothy Pearson730a0432015-10-16 13:51:51 -0500467 { 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500468 0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
469 IsocPreqCBC = 0x0,
470 IsocReqCBC = 0x1,
471 ProbeCBC = 0x7,
472 DnPreqCBC = 0x2,
473 UpPreqCBC = 0x1,
474 DnReqCBC = 0x1,
475 UpReqCBC = 0x1 */
Timothy Pearson730a0432015-10-16 13:51:51 -0500476
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500477 { 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
478 0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
479 Sri2XbarFreeRspDBC = 0x0,
480 Sri2XbarFreeXreqDBC = 0x9,
481 Sri2XbarFreeRspCBC = 0x0,
482 Sri2XbarFreeXreqCBC = 0x9,
483 Xbar2SriFreeListCBC = 0x14 */
484
485 { 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL,
486 0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
487 Sri2XbarFreeRspDBC = 0x0,
488 Sri2XbarFreeXreqDBC = 0x9,
489 Sri2XbarFreeRspCBC = 0x0,
490 Sri2XbarFreeXreqCBC = 0x9,
491 Xbar2SriFreeListCBC = 0x14 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000492
493 /* Errata 281 Workaround */
494 { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
495 AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
496
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500497 { 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
498 0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0,
499 SrqExtFreeListBC = 0x8,
500 Sri2XbarFreeRspDBC = 0x0,
501 Sri2XbarFreeXreqDBC = 0xd,
502 Sri2XbarFreeRspCBC = 0x0,
503 Sri2XbarFreeXreqCBC = 0xf,
504 Xbar2SriFreeListCBC = 0x16 */
Timothy Pearson730a0432015-10-16 13:51:51 -0500505
Marc Jones99fd2a32009-05-14 23:42:41 +0000506 { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Marc Jonesc74e3622008-04-22 23:09:34 +0000507 0x00070814, 0x007FFF1F },
508
Marc Jones99fd2a32009-05-14 23:42:41 +0000509 { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000510 0x00800756, 0x00F3FFFF },
511
Marc Jones99fd2a32009-05-14 23:42:41 +0000512 { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Marc Jonesc74e3622008-04-22 23:09:34 +0000513 0x00C37756, 0x00F3FFFF },
514
Marc Jones99fd2a32009-05-14 23:42:41 +0000515 { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Marc Jonesc74e3622008-04-22 23:09:34 +0000516 0x00000036, 0x000000FF },
517
Timothy Pearson965704a2015-08-07 19:04:49 -0500518 { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
519 0x00a11755, 0x00f3ffff },
520
Marc Jonesc74e3622008-04-22 23:09:34 +0000521 /* Errata 281 Workaround */
522 { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
523 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
Elyes HAOUAS9d759572018-05-28 15:41:12 +0200524 /* [3:0] RspTok = 0001b */
Marc Jonesc74e3622008-04-22 23:09:34 +0000525
Timothy Pearson730a0432015-10-16 13:51:51 -0500526 { 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,
527 0x00000028, 0x000000ff },
528
Marc Jones99fd2a32009-05-14 23:42:41 +0000529 { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
Marc Jonesc74e3622008-04-22 23:09:34 +0000530 0x8000052A, 0xD5FFFFFF },
531
Timothy Pearson965704a2015-08-07 19:04:49 -0500532 /* Core Interface Buffer Count */
533 { 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
534 0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3,
535 L3ToSriReqCBC = 0x4,
536 L3FreeListCBC = default,
537 CpuCmdBufCnt = 0x4 */
538
Marc Jonesc74e3622008-04-22 23:09:34 +0000539 /* ACPI Power State Control Reg1 */
Marc Jones99fd2a32009-05-14 23:42:41 +0000540 { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000541 0xE6002200, 0xFFFFFFFF },
542
Timothy Pearson730a0432015-10-16 13:51:51 -0500543 /* ACPI Power State Control Reg1 */
544 { 3, 0x80, AMD_FAM15_ALL, AMD_PTYPE_ALL,
545 0xe20be200, 0xefefef00 },
546
Marc Jonesc74e3622008-04-22 23:09:34 +0000547 /* ACPI Power State Control Reg2 */
Marc Jones99fd2a32009-05-14 23:42:41 +0000548 { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000549 0xA0E641E6, 0xFFFFFFFF },
550
Timothy Pearson730a0432015-10-16 13:51:51 -0500551 /* ACPI Power State Control Reg2 */
552 { 3, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
553 0x01e200e2, 0xefef00ef },
554
Marc Jones99fd2a32009-05-14 23:42:41 +0000555 { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
Marc Jonesc74e3622008-04-22 23:09:34 +0000556 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
557
Xavi Drudis Ferran0e5d3e12011-02-28 00:18:43 +0000558 { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
559 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */
560
Timothy Pearson730a0432015-10-16 13:51:51 -0500561 { 3, 0xA0, ((AMD_FAM10_ALL | AMD_FAM15_ALL) & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
Xavi Drudis Ferran0e5d3e12011-02-28 00:18:43 +0000562 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000563
564 /* Reported Temp Control Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500565 { 3, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000566 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */
567
568 /* Clock Power/Timing Control 0 Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500569 { 3, 0xD4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000570 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1,
571 [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
572
573 /* Clock Power/Timing Control 1 Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500574 { 3, 0xD8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
575 0x03000010, 0x0F000070 }, /* [6:4] VSRampTime = 1,
576 * [27:24] ReConDel = 3 */
577
578 /* Clock Power/Timing Control 1 Register */
Marc Jones99fd2a32009-05-14 23:42:41 +0000579 { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
Timothy Pearson730a0432015-10-16 13:51:51 -0500580 0x00000006, 0x00000007 }, /* [2:0] VSSlamTime = 6 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000581
582
583 /* Clock Power/Timing Control 2 Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500584 { 3, 0xDC, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000585 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */
586
587
588 /* Extended NB MCA Config Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500589 { 3, 0x180, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jones35b53612008-07-23 21:44:23 +0000590 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7,
591 [9] SyncOnUncNbAryEn = 1 ,
592 [8] SyncOnProtEn = 1,
593 [7] SyncFloodOnTgtAbtErr = 1,
594 [6] SyncFloodOnDatErr = 1,
595 [5] DisPciCfgCpuMstAbtRsp = 1,
596 [1] SyncFloodOnUsPwDataErr = 1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000597
Timothy Pearson99f80422015-08-07 23:58:28 -0500598 /* NB Configuration 2 */
599 { 3, 0x188, AMD_DR_GT_B0, AMD_PTYPE_ALL,
600 0x00000010, 0x00000010 }, /* EnStpGntOnFlushMaskWakeup = 0x1 */
601
602 /* NB Configuration 2 */
603 { 3, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL,
604 0x00000200, 0x00000200 }, /* DisL3HiPriFreeListAlloc = 0x1 */
605
Zheng Bao2ca2f172011-03-28 04:29:14 +0000606 /* errata 346 - Fam10 C2, C3
Marc Jonesaac8dc82009-06-17 15:33:57 +0000607 * System software should set F3x188[22] to 1b. */
Xavi Drudis Ferrancc6244a2010-08-22 19:48:29 +0000608 { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000609 0x00400000, 0x00400000 },
610
Marc Jonesc74e3622008-04-22 23:09:34 +0000611 /* L3 Control Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500612 { 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000613 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */
614
Timothy Pearson16a3a752015-09-03 17:43:52 -0500615 /* Errata 504 workaround */
616 { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
617 0x00040000, 0x00040000 }, /* [18] = 1b */
618
Marc Jonesc74e3622008-04-22 23:09:34 +0000619 /* IBS Control Register */
Timothy Pearson730a0432015-10-16 13:51:51 -0500620 { 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000621 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */
Timothy Pearson730a0432015-10-16 13:51:51 -0500622
623 /* Erratum 619 - Family 15h Bx
624 * System software should set F5x88[14] to 1b. */
625 { 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL,
626 1 << 14, 1 << 14 },
Timothy Pearsonaab3ad22015-08-08 20:31:03 -0500627
628 /* L3 Control 2 */
629 { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
630 0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2,
631 ImplRdAnySubUnavail = 0x1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000632};
633
634
635/*
636 * Default HyperTransport Phy and errata settings.
637 */
638static const struct {
639 u16 htreg; /* HT Phy Register index */
Timothy Pearson730a0432015-10-16 13:51:51 -0500640 uint64_t revision;
Marc Jonesc74e3622008-04-22 23:09:34 +0000641 u32 platform;
642 u32 linktype;
643 u32 data;
644 u32 mask;
645} fam10_htphy_default[] = {
646
Zheng Bao2ca2f172011-03-28 04:29:14 +0000647 /* Errata 344 - Fam10 C2/C3, D0/D1
Marc Jonesaac8dc82009-06-17 15:33:57 +0000648 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
Zheng Bao2ca2f172011-03-28 04:29:14 +0000649 { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000650 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000651 { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000652 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000653 { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000654 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000655 { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000656 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000657 { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000658 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000659 { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000660 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000661 { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000662 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000663 { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000664 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000665 { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000666 0x00000040, 0x00000040 },
667
Zheng Bao2ca2f172011-03-28 04:29:14 +0000668 { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000669 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000670 { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000671 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000672 { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000673 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000674 { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000675 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000676 { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000677 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000678 { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000679 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000680 { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000681 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000682 { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000683 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000684 { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000685 0x00000040, 0x00000040 },
686
Zheng Bao2ca2f172011-03-28 04:29:14 +0000687 /* Errata 354 - Fam10 C2, C3
Marc Jonesaac8dc82009-06-17 15:33:57 +0000688 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
Zheng Bao2ca2f172011-03-28 04:29:14 +0000689 { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000690 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000691 { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000692 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000693 { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000694 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000695 { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000696 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000697 { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000698 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000699 { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000700 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000701 { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000702 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000703 { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000704 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000705 { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000706 0x00000040, 0x00000040 },
707
Zheng Bao2ca2f172011-03-28 04:29:14 +0000708 { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000709 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000710 { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000711 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000712 { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000713 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000714 { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000715 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000716 { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000717 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000718 { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000719 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000720 { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000721 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000722 { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000723 0x00000040, 0x00000040 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000724 { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000725 0x00000040, 0x00000040 },
726
Zheng Bao2ca2f172011-03-28 04:29:14 +0000727 /* Errata 327 - Fam10 C2/C3, D0/D1
Marc Jonesaac8dc82009-06-17 15:33:57 +0000728 * BIOS should set the Link Phy Impedance Register[RttCtl]
729 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
730 * Link Phy Impedance Register[RttIndex]
731 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
Zheng Bao2ca2f172011-03-28 04:29:14 +0000732 { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000733 0x40040000, 0xe01F0000 },
Zheng Bao2ca2f172011-03-28 04:29:14 +0000734 { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000735 0x40040000, 0xe01F0000 },
736
Zheng Bao2ca2f172011-03-28 04:29:14 +0000737 { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000738 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
739
Zheng Bao2ca2f172011-03-28 04:29:14 +0000740 { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000741 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
742
743 { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000744 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
745
Marc Jonesaac8dc82009-06-17 15:33:57 +0000746 { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesc74e3622008-04-22 23:09:34 +0000747 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
748
Timothy Pearson0122afb2015-07-30 14:07:15 -0500749 { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500750 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000751
Timothy Pearson0122afb2015-07-30 14:07:15 -0500752 { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500753 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000754
Timothy Pearson0122afb2015-07-30 14:07:15 -0500755 { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500756 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
Marc Jonesc74e3622008-04-22 23:09:34 +0000757
Timothy Pearson0122afb2015-07-30 14:07:15 -0500758 { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
Elyes HAOUAS9d759572018-05-28 15:41:12 +0200759 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
Marc Jonesc74e3622008-04-22 23:09:34 +0000760
761 /* Link Phy Receiver Loop Filter Registers */
Timothy Pearson0122afb2015-07-30 14:07:15 -0500762 { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
Marc Jonesc74e3622008-04-22 23:09:34 +0000763 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
764 [21:14] LfcMin = 10h */
765
Timothy Pearson0122afb2015-07-30 14:07:15 -0500766 { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
Marc Jonesc74e3622008-04-22 23:09:34 +0000767 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
768 [21:14] LfcMin = 10h */
769
Timothy Pearson0122afb2015-07-30 14:07:15 -0500770 { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
Marc Jonesc74e3622008-04-22 23:09:34 +0000771 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
772 [21:14] LfcMin = 08h */
773
Timothy Pearson0122afb2015-07-30 14:07:15 -0500774 { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
Marc Jonesc74e3622008-04-22 23:09:34 +0000775 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
776 [21:14] LfcMin = 08h */
Marc Jonesaac8dc82009-06-17 15:33:57 +0000777
Timothy Pearson0122afb2015-07-30 14:07:15 -0500778 { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
Marc Jonesaac8dc82009-06-17 15:33:57 +0000779 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
Timothy Pearson0122afb2015-07-30 14:07:15 -0500780 [20:16] RttIndex = 04h */
781
Timothy Pearson0122afb2015-07-30 14:07:15 -0500782 { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
Elyes HAOUAS9d759572018-05-28 15:41:12 +0200783 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
784 P0XmtRdPtr = 0x2
785 P1RcvRdPtr = 0xa
786 P1XmtRdPtr = 0x0 */
Timothy Pearson0122afb2015-07-30 14:07:15 -0500787
788 { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
Elyes HAOUAS9d759572018-05-28 15:41:12 +0200789 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
790 P0XmtRdPtr = 0x2
791 P1RcvRdPtr = 0xa
792 P1XmtRdPtr = 0x0 */
Timothy Pearson0122afb2015-07-30 14:07:15 -0500793
794 { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
Elyes HAOUAS9d759572018-05-28 15:41:12 +0200795 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
796 P0XmtRdPtr = 0x4
797 P1RcvRdPtr = 0xd
798 P1XmtRdPtr = 0x0 */
Timothy Pearson0122afb2015-07-30 14:07:15 -0500799
800 { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
Elyes HAOUAS9d759572018-05-28 15:41:12 +0200801 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
802 P0XmtRdPtr = 0x4
803 P1RcvRdPtr = 0xd
804 P1XmtRdPtr = 0x0 */
Timothy Pearson0122afb2015-07-30 14:07:15 -0500805
806 /* Link Phy Receiver Loop Filter Registers */
807 { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
808 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
809 [21:14] LfcMin = 10h */
810
811 { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
812 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
813 [21:14] LfcMin = 10h */
814
815 { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
816 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
817 [21:14] LfcMin = 08h */
818
819 { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
820 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
821 [21:14] LfcMin = 08h */
822
823 { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
824 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
Timothy Pearson51cfbcd2015-08-02 21:18:29 -0500825 [20:16] RttIndex = 04h */
Timothy Pearson27338462015-09-13 15:54:32 -0500826
827 { 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
828 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d,
829 [7] DfeEn = 0x1 */
830
831 { 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
832 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d,
833 [7] DfeEn = 0x1 */
Marc Jonesc74e3622008-04-22 23:09:34 +0000834};