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Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08001# Warning: This file is included whether or not the if is here.
2# The if controls how the evaluation occurs.
3# (See also src/Kconfig)
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08004
Stefan Reinauera48ca842015-04-04 01:58:28 +02005source "src/cpu/*/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +00006
Furquan Shaikhfd337812014-04-22 15:16:54 -07007if ARCH_X86
8
Kyösti Mälkki0f5e01a2019-08-09 07:11:07 +03009config CAR_GLOBAL_MIGRATION
Aaron Durbinbc17cde2017-04-07 15:20:14 -050010 bool
11 default n
Aaron Durbinbc17cde2017-04-07 15:20:14 -050012 help
Kyösti Mälkki0f5e01a2019-08-09 07:11:07 +030013 This option is selected if there is need to migrate CAR globals.
Aaron Durbinbc17cde2017-04-07 15:20:14 -050014 All stages which use CAR globals can directly access the variables
15 from their linked addresses.
16
Patrick Georgi0588d192009-08-12 15:00:51 +000017config DCACHE_RAM_BASE
18 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000019
20config DCACHE_RAM_SIZE
21 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000022
Timothy Pearsonb5e46552015-06-02 13:47:36 -050023config DCACHE_BSP_STACK_SIZE
24 hex
25
Patrick Georgi0588d192009-08-12 15:00:51 +000026config SMP
27 bool
Myles Watson45bb25f2009-09-22 18:49:08 +000028 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +000029 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000030 help
31 This option is used to enable certain functions to make coreboot
32 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000033
34config MMX
35 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000036 help
37 Select MMX in your socket or model Kconfig if your CPU has MMX
38 streaming SIMD instructions. ROMCC can build more efficient
39 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000040
41config SSE
42 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000043 help
44 Select SSE in your socket or model Kconfig if your CPU has SSE
45 streaming SIMD instructions. ROMCC can build more efficient
46 code if it can spill to SSE (aka XMM) registers.
47
48config SSE2
49 bool
Myles Watson34261952010-03-19 02:33:40 +000050 default n
Aaron Durbinb1aa6112017-06-16 15:20:57 -050051 select SSE
Stefan Reinauera7acc512010-02-25 13:40:49 +000052 help
53 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
54 streaming SIMD instructions. Some parts of coreboot can be built
55 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000056
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000057endif # ARCH_X86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050058
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060059config SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050060 bool
61 default n
62
Martin Roth4c502692015-11-05 08:03:45 -070063config USES_MICROCODE_HEADER_FILES
64 def_bool n
65 select SUPPORT_CPU_UCODE_IN_CBFS
66 help
67 This is selected by a board or chipset to set the default for the
68 microcode source choice to a list of external microcode headers
69
Nico Huberf5ca9222018-11-29 17:05:32 +010070config MICROCODE_BLOB_NOT_IN_BLOB_REPO
71 bool
72 help
73 Selected by platforms that don't maintain microcode updates in the
74 blobs repo yet.
75
76config MICROCODE_BLOB_NOT_HOOKED_UP
77 bool
78 help
79 Selected by platforms that haven't hooked microcode updates up yet.
80
81config MICROCODE_BLOB_UNDISCLOSED
82 bool
83 help
84 Selected by work-in-progress platforms that don't have microcode
85 updates available yet.
86
87config USE_CPU_MICROCODE_CBFS_BINS
88 bool
89 help
90 Automatically selected below to add binary microcode files
91 (`cpu_microcode_bins` in the makefiles) to CBFS.
92
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050093choice
Stefan Reinauer9c29cfa2013-02-27 20:24:11 +010094 prompt "Include CPU microcode in CBFS" if ARCH_X86
Martin Roth4c502692015-11-05 08:03:45 -070095 default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
Nico Huberf5ca9222018-11-29 17:05:32 +010096 default CPU_MICROCODE_CBFS_NONE if MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
97 MICROCODE_BLOB_NOT_HOOKED_UP || \
98 MICROCODE_BLOB_UNDISCLOSED
99 depends on SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500100
Nico Huberf5ca9222018-11-29 17:05:32 +0100101config CPU_MICROCODE_CBFS_DEFAULT_BINS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500102 bool "Generate from tree"
Nico Huberf5ca9222018-11-29 17:05:32 +0100103 select USE_CPU_MICROCODE_CBFS_BINS
104 depends on !(MICROCODE_BLOB_NOT_IN_BLOB_REPO || \
105 MICROCODE_BLOB_NOT_HOOKED_UP || \
106 MICROCODE_BLOB_UNDISCLOSED)
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500107 help
108 Select this option if you want microcode updates to be assembled when
109 building coreboot and included in the final image as a separate CBFS
110 file. Microcode will not be hard-coded into ramstage.
111
Stefan Tauner0ce2b432013-04-01 13:45:44 +0200112 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500113 time with cbfstool, if desired.
114
115 If unsure, select this option.
116
Nico Huberf5ca9222018-11-29 17:05:32 +0100117config CPU_MICROCODE_CBFS_EXTERNAL_BINS
118 bool "Include external microcode binary"
119 select USE_CPU_MICROCODE_CBFS_BINS
120 depends on !CPU_MICROCODE_MULTIPLE_FILES
121 help
122 Select this option if you want to include external binary files
123 in the CPUs native format. They will be included as a separate
124 file in CBFS.
125
126 A word of caution: only select this option if you are sure the
127 microcode that you have is newer than the microcode shipping with
128 coreboot.
129
130 The microcode file may be removed from the ROM image at a later
131 time with cbfstool, if desired.
132
133 If unsure, and applicable, select "Generate from tree"
134
Martin Roth4c502692015-11-05 08:03:45 -0700135config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
136 bool "Include external microcode header files"
Nico Huberf5ca9222018-11-29 17:05:32 +0100137 depends on !CPU_MICROCODE_MULTIPLE_FILES
Martin Roth4c502692015-11-05 08:03:45 -0700138 help
139 Select this option if you want to include external c header files
140 containing the CPU microcode. This will be included as a separate
141 file in CBFS.
142
143 A word of caution: only select this option if you are sure the
144 microcode that you have is newer than the microcode shipping with
145 coreboot.
146
147 The microcode file may be removed from the ROM image at a later
148 time with cbfstool, if desired.
149
Nico Huberf5ca9222018-11-29 17:05:32 +0100150 If unsure, and applicable, select "Generate from tree"
Martin Roth4c502692015-11-05 08:03:45 -0700151
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500152config CPU_MICROCODE_CBFS_NONE
153 bool "Do not include microcode updates"
154 help
155 Select this option if you do not want CPU microcode included in CBFS.
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500156
157 Microcode may be added to the ROM image at a later time with cbfstool,
158 if desired.
159
Nico Huberf5ca9222018-11-29 17:05:32 +0100160 If unsure, and applicable, select "Generate from tree"
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500161
162 The GOOD:
163 Microcode updates intend to solve issues that have been discovered
164 after CPU production. The expected effect is that systems work as
165 intended with the updated microcode, but we have also seen cases where
166 issues were solved by not applying microcode updates.
167
168 The BAD:
169 Note that some operating system include these same microcode patches,
170 so you may need to also disable microcode updates in your operating
171 system for this option to have an effect.
172
173 The UGLY:
174 A word of CAUTION: some CPUs depend on microcode updates to function
175 correctly. Not updating the microcode may leave the CPU operating at
176 less than optimal performance, or may cause outright hangups.
177 There are CPUs where coreboot cannot properly initialize the CPU
178 without microcode updates
179 For example, if running with the factory microcode, some Intel
180 SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
181 will hang when changing the frequency.
182
183 Make sure you have a way of flashing the ROM externally before
184 selecting this option.
185
186endchoice
Jens Rottmann686dc0d2013-02-18 17:26:01 +0100187
Timothy Pearson24e6d042015-10-08 16:58:58 -0500188config CPU_MICROCODE_MULTIPLE_FILES
189 bool
Timothy Pearson24e6d042015-10-08 16:58:58 -0500190 help
191 Select this option to install separate microcode container files into
192 CBFS instead of using the traditional monolithic microcode file format.
Martin Roth4c502692015-11-05 08:03:45 -0700193
194config CPU_MICROCODE_HEADER_FILES
195 string "List of space separated microcode header files with the path"
196 depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER
197 help
198 A list of one or more microcode header files with path from the
199 coreboot directory. These should be separated by spaces.
Martin Roth3eb65ec2016-08-30 16:21:53 -0600200
201config CPU_UCODE_BINARIES
202 string "Microcode binary path and filename"
Nico Huberf5ca9222018-11-29 17:05:32 +0100203 depends on CPU_MICROCODE_CBFS_EXTERNAL_BINS
Martin Roth3eb65ec2016-08-30 16:21:53 -0600204 default ""
205 help
206 Some platforms have microcode in the blobs directory, and these can
207 be hardcoded in the makefiles. For platforms with microcode
208 binaries that aren't in the makefile, set this option to pull
209 in the microcode.
210
211 This should contain the full path of the file for one or more
212 microcode binary files to include, separated by spaces.
213
214 If unsure, leave this blank.