blob: d7fcbd6daff0215271a287b91aeab159e064b882 [file] [log] [blame]
Alexander Couzens77103792015-04-16 02:03:26 +02001/*
Martin Roth669e1552019-07-28 18:39:33 -06002 * This file is part of the coreboot project.
Alexander Couzens77103792015-04-16 02:03:26 +02003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
Alexander Couzens77103792015-04-16 02:03:26 +020012 */
13
14#include "sata.h"
15
16#include <arch/acpi.h>
17#include <arch/acpigen.h>
18
19/* e.g.
20 * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3);
21 * generates:
22 * Scope (\_SB.PCI0.SATA)
23 * {
24 * Device (PR00)
25 * {
26 * Name (_ADR, 0x0000FFFF) // _ADR: Address
27 * }
28 *
29 * Device (PR01)
30 * {
31 * Name (_ADR, 0x0001FFFF) // _ADR: Address
32 * }
33 * }
34 *
35 */
36void generate_sata_ssdt_ports(const char *scope, uint32_t enable_map)
37{
38 int i;
39 uint32_t bit;
40 char port_name[4] = "PR00";
41
42 acpigen_write_scope(scope);
43
44 /* generate a device for every enabled port */
45 for (i = 0; i < 32; i++) {
46 bit = 1 << i;
47 if (!(bit & enable_map))
48 continue;
49
50 port_name[2] = '0' + i / 10;
51 port_name[3] = '0' + i % 10;
52
53 acpigen_write_device(port_name);
54
55 acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000);
56 acpigen_pop_len(); /* close PRT%d */
57 }
58
59 acpigen_pop_len(); /* close scope */
60}