| Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | Scope(\) |
| 23 | { |
| 24 | // IO-Trap at 0x800. This is the ACPI->SMI communication interface. |
| 25 | |
| 26 | OperationRegion(IO_T, SystemIO, 0x800, 0x10) |
| 27 | Field(IO_T, ByteAcc, NoLock, Preserve) |
| 28 | { |
| 29 | Offset(0x8), |
| 30 | TRP0, 8 // IO-Trap at 0x808 |
| 31 | } |
| 32 | } |
| Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 33 | |
| 34 | /* Device Resource Consumption */ |
| 35 | Device (PDRC) |
| 36 | { |
| 37 | Name (_HID, EISAID("PNP0C02")) |
| 38 | Name (_UID, 1) |
| 39 | |
| 40 | Name (PDRS, ResourceTemplate() { |
| 41 | Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) |
| 42 | Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) |
| 43 | Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) |
| 44 | Memory32Fixed(ReadWrite, IO_BASE_ADDRESS, IO_BASE_SIZE) |
| 45 | Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 46 | Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) |
| 47 | Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) |
| 48 | Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) |
| 49 | Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
| 50 | #if CONFIG_CHROMEOS_RAMOOPS |
| 51 | Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, |
| 52 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) |
| 53 | #endif |
| 54 | }) |
| 55 | |
| 56 | // Current Resource Settings |
| 57 | Method (_CRS, 0, Serialized) |
| 58 | { |
| 59 | Return(PDRS) |
| 60 | } |
| 61 | } |