Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 17 | #include <bootblock_common.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 18 | #include <stdint.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 19 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 22 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 2a3f9f5 | 2019-08-26 13:59:54 +0300 | [diff] [blame] | 23 | #include <superio/smsc/sio1007/sio1007.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 24 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 25 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | cf0e902 | 2016-02-10 03:09:46 +0100 | [diff] [blame] | 26 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 27 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 28 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 29 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 30 | #define SIO_PORT 0x164e |
| 31 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 32 | void mainboard_pch_lpc_setup(void) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 33 | { |
Elyes HAOUAS | 4b73fa9 | 2018-06-08 19:00:44 +0200 | [diff] [blame] | 34 | pci_devfn_t dev = PCH_LPC_DEV; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 35 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 36 | /* Enable SuperIO + PS/2 Keyboard/Mouse */ |
| 37 | u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 38 | pci_write_config16(dev, LPC_EN, lpc_config); |
| 39 | |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 40 | /* Enable COM1 */ |
| 41 | if (sio1007_enable_uart_at(SIO_PORT)) { |
| 42 | pci_write_config16(dev, LPC_EN, |
| 43 | lpc_config | COMA_LPC_EN); |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 44 | } |
| 45 | } |
| 46 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 47 | void bootblock_mainboard_early_init(void) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 48 | { |
Marc Jones | c4b6f3b | 2013-11-05 17:47:37 -0700 | [diff] [blame] | 49 | const u16 port = SIO_PORT; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 50 | const u16 runtime_port = 0x180; |
| 51 | |
| 52 | /* Turn on configuration mode. */ |
| 53 | outb(0x55, port); |
| 54 | |
| 55 | /* Set the GPIO direction, polarity, and type. */ |
| 56 | sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); |
| 57 | sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); |
| 58 | sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); |
| 59 | |
| 60 | /* Set the base address for the runtime register block. */ |
| 61 | sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); |
| 62 | sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); |
| 63 | |
| 64 | /* Turn on address decoding for it. */ |
| 65 | sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); |
| 66 | |
| 67 | /* Set the value of GPIO 10 by changing GP1, bit 0. */ |
| 68 | u8 byte; |
| 69 | byte = inb(runtime_port + 0xc); |
| 70 | byte |= (1 << 0); |
| 71 | outb(byte, runtime_port + 0xc); |
| 72 | |
| 73 | /* Turn off address decoding for it. */ |
| 74 | sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); |
| 75 | |
| 76 | /* Turn off configuration mode. */ |
| 77 | outb(0xaa, port); |
| 78 | } |
| 79 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 80 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 81 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 82 | struct pei_data pei_data_template = { |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 83 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 84 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 85 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 86 | .epbar = DEFAULT_EPBAR, |
| 87 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 88 | .smbusbar = SMBUS_IO_BASE, |
| 89 | .wdbbar = 0x4000000, |
| 90 | .wdbsize = 0x1000, |
| 91 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 92 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 93 | .pmbase = DEFAULT_PMBASE, |
| 94 | .gpiobase = DEFAULT_GPIOBASE, |
| 95 | .thermalbase = 0xfed08000, |
| 96 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 97 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 98 | .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, |
| 99 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 100 | .ec_present = 0, |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 101 | // 0 = leave channel enabled |
| 102 | // 1 = disable dimm 0 on channel |
| 103 | // 2 = disable dimm 1 on channel |
| 104 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | ea4ae2f | 2014-05-24 02:08:04 +1000 | [diff] [blame] | 105 | .dimm_channel0_disabled = 2, |
| 106 | .dimm_channel1_disabled = 2, |
| 107 | .max_ddr3_freq = 1600, |
| 108 | .usb_port_config = { |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 109 | { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ |
| 110 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 111 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 112 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 113 | { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ |
| 114 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 115 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 116 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 117 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 118 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 119 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 120 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 121 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 122 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 123 | }, |
| 124 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 125 | *pei_data = pei_data_template; |
| 126 | } |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 127 | |
Vladimir Serbinenko | cf0e902 | 2016-02-10 03:09:46 +0100 | [diff] [blame] | 128 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 129 | /* enabled power usb oc pin */ |
| 130 | { 1, 0, 0 }, /* P0: Front port (OC0) */ |
| 131 | { 1, 0, 1 }, /* P1: Back port (OC1) */ |
| 132 | { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ |
| 133 | { 1, 0, -1 }, /* P3: MMC (no OC) */ |
| 134 | { 1, 0, 2 }, /* P4: Front port (OC2) */ |
| 135 | { 0, 0, -1 }, /* P5: Empty */ |
| 136 | { 0, 0, -1 }, /* P6: Empty */ |
| 137 | { 0, 0, -1 }, /* P7: Empty */ |
| 138 | { 1, 0, 4 }, /* P8: Back port (OC4) */ |
| 139 | { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ |
| 140 | { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ |
| 141 | { 0, 0, -1 }, /* P11: Empty */ |
| 142 | { 1, 0, 6 }, /* P12: Back port (OC6) */ |
| 143 | { 1, 0, 5 }, /* P13: Back port (OC5) */ |
| 144 | }; |
| 145 | |
Peter Lemenkov | 498f1cc | 2019-02-07 10:48:10 +0100 | [diff] [blame] | 146 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 147 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 148 | read_spd(&spd[0], 0x50, id_only); |
| 149 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | cf0e902 | 2016-02-10 03:09:46 +0100 | [diff] [blame] | 150 | } |
| 151 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 152 | int mainboard_should_reset_usb(int s3resume) |
| 153 | { |
| 154 | return !s3resume; |
Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame] | 155 | } |